Low noise circuit and applications thereof

Details Low noise circuit and applications thereof Low noise circuit and applications thereof

2004-10-05

2008-11-25

Ahn, Sam K (Department: 2611)

Pulse or digital communications

Receivers

Interference or noise reduction

Reexamination Certificate

active

07457380

ABSTRACT:
A low noise circuit includes a clocked circuit and an impedance trap circuit. The clocked circuit includes a clock input, an input, an output, a power supply connection, and a power return connection. The clock input is operably coupled to receive a clock signal. The clocked circuit provides an output signal at the output based on an input signal at the input and a transition of the clock signal. The power supply connection is operably coupled to a power supply and the power return is operably coupled to a circuit ground. The impedance trap circuit is operably coupled to the power supply connection and the power return connection, wherein the impedance trap circuit attenuates a harmonic signal component of at least one of the input signal, the clock signal, and the output signal.

REFERENCES:
patent: 5138203 (1992-08-01), Ono et al.
patent: 5912596 (1999-06-01), Ghoshal
patent: 5963856 (1999-10-01), Kim
patent: 6396316 (2002-05-01), Cruz et al.
patent: 2002/0101284 (2002-08-01), Kee et al.
patent: 2002/0105384 (2002-08-01), Dent
patent: 2004/0224658 (2004-11-01), Borremans

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