Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-04-23
2002-12-03
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S437000, C326S027000
Reexamination Certificate
active
06489815
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a low-noise buffer circuit, and more particularly, to a low-noise buffer circuit which reduces noise, stabilizes output voltage and reduces variation of current flowing through itself.
2. Description of Related Art
Conventionally, as such low-noise buffer circuit, an output buffer for impedance matching in a transmission path, a CMOS circuit having a transistor serving as a high resistor connected to an inverter are known. These buffer circuits are provided for suppressing a peak current (the maximum current upon occurrence of a change in input). These buffer circuits are grouped into two types. One type is circuits to feed a short circuit current through a CMOS circuit and the other type is circuits without short circuit current.
The former type circuits include a circuit using a termination resistor and a circuit in a sense amplifier driving circuit of semiconductor memory as disclosed in Japanese Kokai No. Hei 4-30389 where a gate of a driving transistor is provided with voltage lower than a threshold voltage of the transistor so that the transistor is gradually turned on. Besides, a circuit in an output driver circuit as disclosed in Japanese Kokai No. Hei 1-165225 has a transistor to function as a high resistor or week current power supply connected to an inverter.
On the other hand, the latter circuits include an output driver as disclosed in Japanese Kokai No. Hei 134016 having a circuit where the occurrence of short circuit current is completely prevented by first operating a transistor which takes an off state from an on state, and a circuit where the short circuit current is eliminated by shifting operation timing of charged/discharged transistor to reduce the peak current. Besides, a circuit as disclosed in Japanese Kokai No. Hei 2-220294 has a precharge circuit that is controlled by a signal corresponding to an output signal level and prevents occurrence of short circuit current, so as to enable high-speed reading or to reduce the peak current, and a circuit as disclosed in Japanese Kokai No. Hei 1185022 eliminates the short circuit current by controlling the operation timing with inverters having different logical thresholds.
In any case, the conventional buffer circuits feed or eliminate the short circuit current to suppress the peak current. In a CMOS inverter, if noise due to operation switching is to be reduced, the short circuit current is fed while sacrificing current consumption to a degree. On the other hand, if reduction of the current consumption occupies a higher priority than the reduction of the noise, the short circuit current is eliminated while sacrificing occurrence of noise due to impedance mismatch in a transmission path or switching noise.
FIG. 5
is a diagram of a prior art buffer circuit where an output side is terminated. As shown in
FIG. 5
, the buffer circuit has a CMOS inverter circuit
2
comprising a PMOS transistor
21
and an NMOS transistor
22
with respective gates connected to an input terminal
11
. A source of the PMOS transistor
21
is connected to a power supply VDD, and a source of the NMOS transistor
22
is connected to the ground GND. Both drains are connected to an output terminal
12
. The output terminal
12
supplies a predetermined voltage VDD/
2
via a transmission line
5
and a termination resistor R.
In this case, a current is constantly flowed through the transmission path
5
and the termination resistor R via the PMOS transistor
21
or the NMOS transistor
22
of the CMOS circuit
2
, and reflection noise is suppressed by obtaining impedance matching in the transmission path while sacrificing such constant current.
FIG. 6
is a diagram of AC operation characteristics representing respective levels of input/output voltages and currents in the CMOS circuit in FIG.
5
. The vertical axis represents potential and current, and the horizontal axis represents time. In
FIG. 6
, VIN denotes an input voltage applied to the input terminal
11
; VOUT, an output voltage which appears in the output terminal
12
upon application of the input voltage VIN; IV, a current which flows from the power supply VDD via the PMOS transistor
21
and via the output terminal
12
and the NMOS transistor
22
through the VDD/
2
; IG, a current which flows from the output terminal
12
via the NMOS transistor
22
and from the power supply VDD/
2
via the PMOS transistor
21
through the GND.
Accordingly, a whisker-like variation occurs in the currents IV and IG when the power supply is turned on (time: 0.0 nS) and upon inversion of the CMOS circuit
2
(approximately 22.0 nS). Further, in case of output buffer having a termination resistor, the maximum current variation (p-p) is 17.5 mA, and the through rate of output waveform is 1.0 V
S.
In the above-described Japanese Kokai No. Hei 1-165225, a high resistor and a weak current power supply are connected between the CMOS circuit
2
and the power supply VDD and the GND to suppress such noise and short circuit current upon inversion of the inverter.
As above-described, the related low-noise buffer circuits suppresses reflection noise by sacrificing constantly-flowing current and switching noise by connecting high-resistor to a weak current power supply.
That is, in interface techniques in recent years represented by an output buffer having a termination resistor, a low-amplitude signal is obtained by divided voltage by the termination resistor. For this purpose, such interface has a high power-supply voltage in consideration of divided voltage. That is, the interface increases a voltage to a high voltage and then reduces the voltage (to a low-amplitude). However, such repetition of voltage increase/decrease lowers circuit efficiency. Further, in acquisition of high-speed operation in a buffer which forms an interface in recent years, to reduce noise due to impedance mismatch in a transmission path, the buffer usually has a termination resistor. In such case, a large constant current by the termination resistor occurs, and the current greatly varies upon switching.
More particularly, in recent interface techniques, a bus width increases and the number of operations increases. Accordingly, in high-speed operation, simultaneous operation timings are further concentrated, so that simultaneous operation noise increases. Further, a large constant current which occurs by a termination resistor connected to an output terminal varies upon switching operation, and noise caused by the current increases.
Accordingly, in the related buffer circuits, as a countermeasure for the increase in simultaneous operation noise and delay variation due to the simultaneous operation noise, or in use of termination resistor, a large constant current varies upon switching, which increases radiation noise.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a low-noise buffer circuit which suppress such noises as described above.
Another object of the present invention is to provide a low-noise buffer circuit which suppresses a variation of current, whereby noise can be reduced.
A low-noise buffer circuit according to the present invention includes a first circuit having an input terminal provided with an input signal, an output terminal supplying an output signal, and first and second terminals; a first current source connected between a first potential source and the first terminal; a the current source connected between a second potential source and the second; and a first component serving as a resistor and connected between the first and second current sources in parallel to the first circuit.
These and other objects of the present invention will be apparent to those of skill in the art from the appended claims when read in light of the following specification and accompanying figures.
REFERENCES:
patent: RE31749 (1984-11-01), Yamashiro
patent: 5483186 (1996-01-01), Miller et al.
patent: 1-34016 (1989-02-01), None
patent: 1-165225 (1989-06-01), None
patent: 1-185022 (1989-07-01), None
patent: 2-2202
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