Low noise BICMOS circuit

Details Low noise BICMOS circuit Low noise BICMOS circuit

1992-05-06

1994-02-15

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307456, 307443, H03K 1760, H03K 1902, H03K 1920, H03K 1716

Patent

active

052870219

ABSTRACT:
A plurality of transistors (22, 23, 27) are utilized to provide a low noise high-to-low transition (40) on an output (19) of a circuit (10). The transistors (22, 23, 27) are sequentially enabled to vary a rate of change of output current thereby minimizing noise created by the high-to-low transition (40). A first transistor (22) is enabled to provide a low rate of change. Subsequently, a second transistor (23) is enabled to provide a higher rate of change. Then, just prior to disabling the second transistor (23) a third transistor (27) is enabled to provide a d.c. level.

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M. Shoji, "CMOS Digital Circuit Technology", Prentice Hall, N.J., 1988, pp. 79-83.

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