Low noise biasing technique

Details Low noise biasing technique Low noise biasing technique

2001-11-13

2002-09-17

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C327S537000

Reexamination Certificate

active

06452370

ABSTRACT:

BACKGROUND
One of the common ways to provide gate bias to an enhancement mode Field Effect Transistor (eFET) is to use a current mirror. The current mirror is itself a source of unwanted noise. In the prior art, using the largest value resistor possible to couple from the current mirror to the amplifier transistor has minimized this noise. This resistor (Ri) can cause a reduction in the power handling capacity of the amplifier transistor. When the input signal is large enough, the amplifier transistor attempts to draw more current. This action requires more current through the gate of the field effect transistor (FET), dropping voltage across Ri. As the voltage increases across Ri, the voltage available to the input of the amplifier transistor is reduced. The voltage at the input sets the current through the amplifier, and so this reduction lowers the power handling capacity of the amplifier. This is a significant source of distortion. The distortion is another noise source.
A large resistor minimizes the noise injected into the amplifier from the bias network but a small resistor minimizes the noise due to distortion. The compromise can be difficult to find.
SUMMARY
In a first embodiment, a first transistor has a drain and gate tied together at a first node. Its source is connected to ground. A current-setting resistor connects between the first node and an RF output. A first capacitor connects between node A and ground. A first inductor connects between an RF input and node A. The second transistor has a drain connected to the RF output and a source connected to ground. A second inductor connects between the gate of the second transistor and the RF input. A third inductor interposes power and the RF output. A second capacitor interposes power and ground.
In a second embodiment, a first transistor has a drain and gate tied together at node B. The source of the first transistor is connected to ground. A first capacitor connects between node B and ground. A second transistor has a drain connected to a RF output and a source connected to ground. A current setting resistor interposes power and node B. A first inductor interposes node B and a RF input. A second inductor connects between the gate of the second transistor and the RF input. A third inductor interposes power and the RF output. A second capacitor interposes power and ground.
In both embodiments, the first and second transistors are formed on a unitary substrate. The current setting resistor may be optionally integrated onto the unitary substrate.


REFERENCES:
patent: 4961006 (1990-10-01), Pace et al.
patent: 5486787 (1996-01-01), Maekawa

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