Oscillators – With frequency adjusting means – With voltage sensitive capacitor
Reexamination Certificate
2001-09-27
2003-07-22
Young, Brian (Department: 2819)
Oscillators
With frequency adjusting means
With voltage sensitive capacitor
C331S014000, C331S016000
Reexamination Certificate
active
06597250
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invent ion relates to a frequency synthesizer having a fractional divider and a corresponding frequency synthesizing method.
The invention more particularly relates to a low-noise frequency synthesizer permitting a precise adjustment of the frequency and capable of rapidly switching between various selected frequencies one after the other.
Such a frequency synthesizer may be used in various types of radio circuits and, more particularly, in receiving and/or transmitting stages of these circuits. By way of example the frequency synthesizer according to the invention may be used in cordless telephony equipment such as portable telephones.
BACKGROUND OF THE INVENTION
The appended
FIGS. 1 and 2
illustrate an integral-value adjustable frequency synthesizer and a fractional-value adjustable frequency synthesizer. A fractional-value adjustable frequency synthesizer is understood to be a frequency synthesizer whose frequency can be adjusted by integral or non-integral multiples of a reference frequency. Such devices are known per se and illustrated, for example, by the documents (1), (2) and (3), whose complete references are stated at the end of the description.
FIG. 1
indicates the basic structure of a frequency synthesizer, which is constructed around a phase-locked loop
10
. The phase-locked loop comprises, in essence, a voltage-controlled oscillator
12
, a frequency divider
14
, a phase-frequency comparator
16
and a loop filter
18
.
The voltage-controlled oscillator
12
, also referred to as a <<VCO oscillator>> in the following text, delivers an output signal whose frequency can be increased or reduced as a function of a control voltage applied to its input. This control voltage is produced by the phase-frequency comparator
16
, which is connected to the input of the VCO oscillator
12
via the loop filter
18
.
The phase-frequency comparator
16
compares the frequency (or phase) of a signal delivered by the frequency divider
14
and the frequency of a reference signal delivered in the example of the Figure by a quartz device
20
. When the frequency of the signal delivered by the frequency divider is lower than that of the reference signal, the phase-frequency comparator associated to the loop filter
18
produces a voltage instructing the frequency of the VCO oscillator
12
to be increased. Conversely, the frequency of the VCO oscillator is reduced when the frequency of the signal delivered by the frequency divider is higher than that of the reference signal.
The frequency divider
14
is a device constructed around a certain number of flip-flops and can thus divide the frequency of the signal of the VCO oscillator
12
only by integral values. The dividing ratio, which is adjustable by integral values, is an integer referred to as N. An adjusting input, indicated by an arrow
22
, enables to fix the value N.
The frequency of the VCO oscillator, referred to as F
VCO
is thus such that:
F
VCO
=N*F
ref
, (1)
where F
REF
is the frequency of the reference signal delivered by the quartz device
20
.
It is observed that a modification by unity of the value of the dividing ratio N (integral) provokes a variation equal to Fref of the frequency of the VCO oscillator. Accordingly, it is impossible to adjust the frequency of the VCO oscillator
12
with a resolution higher than Fref. In the case where the frequency of the reference signal is high, this resolution may turn out to be insufficient.
A much finer adjustment of the frequency of the output signal of the loop
10
, that is to say, of the frequency of the signal delivered by the VCO oscillator
12
, may be obtained with a frequency synthesizer in accordance with FIG.
2
.
The frequency synthesizer shown in
FIG. 2
comprises a phase-locked loop
10
which includes the same elements as those of loop
10
of FIG.
1
.
The frequency divider
14
, on the other hand, has not only an adjusting input
22
for fixing the value N of the dividing ratio, but also a switch input
24
for switching the dividing ratio between two or more consecutive values around the value N. In the example of
FIG. 2
, the switch input
24
of the frequency divider
14
enables to switch the dividing ratio between two values, which are N and N+1.
The switch input
24
is connected to a sigma-delta modulator
40
and, to be more precise, to an overflow-carry terminal
32
of this modulator.
The sigma-delta modulator
30
which, in the example of the Figure, is a first-order digital modulator with a word adder
31
, has a first digital input
34
for an adjusting instruction referred to as K. The adjusting instruction is added to a digital value delivered by a shift register
36
of the modulator. The register
36
is clocked by the output signal of the frequency divider
14
, and receives the output of the word adder
31
. It is connected to a second digital input
38
of the adder. When the sum of the adjusting instruction and of the output of the register
36
is lower than a digital capacity of the adder
31
, the overflow-carry adopts the logic 0 value, for example. On the other hand, when the sum is higher than the capacity of the adder
31
, the overflow-carry adopts the complementary logic 1 value in that case.
The frequency divider
14
is arranged for performing a frequency division with a first dividing ratio when its switch input
24
receives the first logic state and for performing a division with a second dividing ratio which is different from +/−1, when the input
24
receives the second switching state.
In the example described, the dividing ratio is N for a logic 0 state and N+1 for a logic 1 state.
Although at any instant the dividing ratio of the frequency divider is an integer, the repeated switching of the ratio between N and N+1 enables to obtain a resulting mean dividing ratio comprised between these two values, that is to say, a non-integral ratio.
In a more precise way, one has:
Fvco
=
1
T
N
+
T
N
+
1
[
T
N
*
N
*
F
ref
+
T
N
+
1
*
(
N
+
1
)
*
F
ref
]
that
is
,
Fvco
=
[
N
+
T
N
+
1
T
N
+
T
N
+
1
]
*
F
ref
In these expressions, T
N
and T
N+1
are the periods during which the dividing ratio is equal to N and N+1, respectively.
Considering that the adjusting instruction K applied to the first input
34
of the sigma-delta modulator is coded in L bits, and that the maximum capacity of the adder is 2
L
−1, a fractional part of the dividing ratio equal to K/2
L
can be defined. The fractional component K/2
L
is further denoted k in the following of the text. One has:
Fvco
=
[
N
+
K
2
L
]
*
F
ref
(
2
)
For low values of the adjusting instruction (K≡0) the output frequency is close to F
ref
*(N) and for high values of the adjusting instruction (K≡2
L
) the output frequency is close to F
ref
*(N+1).
Accordingly, it is possible to continuously adjust the frequency of the phase-locked loop between two values fixed by the choice of the dividing ratio N applied to the adjusting input
22
of the frequency divider
14
and by the choice of the adjusting instruction K applied to the sigma-delta modulator.
In the conventional phase-locked loops shown in
FIG. 1
, the oscillation frequency of the voltage-controlled oscillator may be adjusted via frequency “steps” whose value is F
ref
. The “step” thus corresponds to a variation of the dividing ratio from N to N+1 or from N to N−1. This clearly appears when reference is made to formula (1) indicated previously.
In order to obtain a relatively precise adjustment of the frequency of the loop, for example, the value of the frequency Fref of the reference signal is preferably chosen to be low. By way of a simple example, the frequency F
ref
, and thus the adjusting step, may be of the order of 200 kHz.
It may also be observed that a low reference frequency leads to retaining high values N of the dividing ratio. Indeed, it would be recollected that the frequency of the voltage-controlled oscil
Biren Steven R.
Koninklijke Philips Electronics , N.V.
Nguyen John B
Young Brian
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