Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit
Reexamination Certificate
2001-07-20
2003-01-14
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Nonlinear amplifying circuit
C327S556000, C330S253000, C330S254000
Reexamination Certificate
active
06507239
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to input amplifiers, and more particularly, to input amplifiers that have low noise and low offset output signals and are compatible with standard submicron CMOS processes.
An input amplifier is a type of amplifier that may be used as an input stage for circuit applications such as an operational amplifier or a comparator.
FIG. 1
illustrates prior input amplifier
10
comprising transistors made from standard submicron CMOS processes. Input voltage V
IN
is applied to the bases of PNP bipolar junction transistors (BJTs) Q
L1
and Q
L2
. BJTs Q
L1
and Q
L2
comprise a differential pair amplifier, with a bias current (equal to I) from current source I
1
and a single ended output at the gate of n-channel MOSFET M
3
. The emitters of BJTs Q
L1
and Q
L2
are coupled to a current mirror circuit comprising n-channel MOSFETs M
1
and M
2
. The drain of M
2
is coupled to the gate of transistor M
3
. Transistor M
3
is a common-source amplifier that provides voltage gain to the input signal to produce output voltage V
OUT
at the drain of M
3
. Transistor M
3
is biased from current source I
2
, at a current equal to I.
FIGS. 3A-3B
illustrates top down and cross sectional layout views, respectively, of PNP BJTs Q
L1
and Q
L2
. BJTs Q
L1
and Q
L2
are each lateral PNP BJTs that may be fabricated using standard submicron CMOS process steps that are used to fabricate p-channel MOSFETs. Each of BJTs Q
L1
and Q
L2
includes a parasitic vertical PNP BJT, Q
S1
and Q
S2
, respectively, as shown in FIGS.
1
and
3
A-
3
B. The lateral PNP BJTs (Q
L1
and Q
L2
) and their parasitic vertical PNP BJTs (Q
S1
and Q
S2
) share the same base and emitter semiconductor regions, but have different collector semiconductor regions as shown in
FIGS. 3A-3B
. Lateral BJTs Q
L1
and Q
L2
each have a collector terminal coupled to a P+ collector region
32
that surrounds a P+ emitter region
31
as shown in
FIGS. 3A-3B
. Vertical BJTs Q
S1
and Q
S2
each have a collector terminal coupled to a P+ region
33
that is tied to the P-substrate region of the device, which is grounded.
FIG. 3C
illustrates a schematic of the lateral and vertical PNP BJTs of
FIGS. 3A-3B
.
Referring to
FIG. 1
, a current equal to I/
2
flows through each of transistors Q
L1
and Q
L2
when V
IN
equals zero, assuming that no current flows into transistors Q
S1
, and Q
S2
. Transistor M
3
is sized by design so that it has a channel width-to-length (W/L) ratio that is 2 times the channel W/L ratio of n-channel MOSFETs M
1
and M
2
. The W/L ratio of transistor M
3
relative to the W/L ratio of transistors M
1
and M
2
determnines the current through transistor M
3
. Thus, when I/
2
flows through each of transistors M
1
and M
2
, a current equal to I flows through M
3
, causing V
OUT
to be accurate with a low signal-to-noise ratio.
However, a significant parasitic current i
EQS1
and i
EQS2
does flow into the emitters of parasitic transistors Q
S1
and Q
S2
. The parasitic current causes the current through transistors M
1
and M
2
to be less than I/
2
. Because the current through transistor M
3
is still I, V
DS
of M
1
and V
DS
of M
2
are no longer equal and the circuit is unbalanced, causing an offset voltage with respect to the amplifier inputs or an inaccurate V
OUT
. Therefore, transistors Q
S1
, and Q
S2
cause prior art amplifier
10
to have a systematic offset voltage at V
OUT
.
It would therefore be desirable to provide a CMOS compatible input amplifier that improves upon prior art input amplifier
10
by reducing output offset to provide a more accurate amplified signal V
OUT
.
BRIEF SUMMARY OF THE INVENTION
The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor.
The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET. The current through the second amplifier determines the output signal V
OUT
. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors. By providing a proportional current to the second amplifier, input amplifiers of the present invention output an accurate, low input offset voltage amplified signal V
OUT
.
REFERENCES:
patent: 5867778 (1999-02-01), Khoury et al.
patent: 6084472 (2000-07-01), Gilbert
patent: 6232839 (2001-05-01), Honda
Cahill Steven J.
I-XYS Corporation
Lam Tuan T.
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