Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2003-04-29
2004-11-23
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
C330S311000
Reexamination Certificate
active
06822518
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to radio frequency electronics, and more specifically, to a low noise amplifier.
2. Description of the Prior Art
Low noise amplifiers (LNAs) are used in a wide variety of applications such as RF communication systems including wireless computer networks and mobile phones. As demand for these systems becomes widespread, the need to improve and refine LNAs increases with the aim of improving performance, reliability, and cost.
FIG. 1
illustrates a conventional LNA
10
, in which a dashed line separates on-chip components from off-chip ones. The LNA
10
includes a transistor
22
having a drain applied with a supply voltage Vdd through a first inductor
26
. An input RF signal is applied to a gate of the transistor
22
through a second inductor
28
, while output of the LNA
10
is taken from the drain of the transistor
22
. The gate of the transistor
22
is further connected to a current mirror circuit
24
, which provides a predetermined bias current. A source of the transistor
22
is connected to a ground
12
via an on-chip node Q that also grounds the current mirror circuit
24
. Operation of the LNA
10
is well known in the art with the input RF signal being amplified according to the voltage Vdd, the bias current, and the inductances of the inductors
26
,
28
.
When the LNA
10
is manufactured according to CMOS processes, all the above components are installed on-chip except for the single off-chip ground
12
. U.S. Pat. No. 5,574,405, which is incorporated herein by reference, thoroughly describes the advantages of on-chip components for an LNA similar to that of FIG.
1
. Despite these advantages, the on-chip connection at node Q results in poor isolation and stability, and increased susceptibility to noise. Other shortcomings of the LNA
10
include a relatively narrow bandwidth and increased chip area from inductor
28
.
Another prior art LNA is described in U.S. Pat. No. 6,198,352, which is incorporated herein by reference. Among other components, such an LNA includes a resistance in place of the second inductor
28
of the LNA
10
. Hence, further disadvantages of this type of LNA include a DC-mode resistance and corresponding power loss, and an uncertainty in the drain voltage of the transistor
22
or its equivalent.
In summary, prior art LNAs, such as the LNA
10
, are in need of improvements regarding performance and manufacture in order to provide effective functionality to modern communications devices.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a low noise amplifier having improved structure and manufacturability to solve the above prior art problems.
Briefly summarized, the claimed invention includes a first transistor, a second transistor, an inductor, and a first resistor. The gate of the first transistor is connected to an RF input node, and the source is connected to a first ground node. The source of the second transistor is connected to a drain of the first transistor. The drain of the second transistor is connected to an RF output node, while the gate is connected to a first bias voltage. Further provided is a current mirror circuit connected to the gate of the first transistor for providing a predetermined bias current. The inductor is connected between the RF output node and a supply voltage node. The first resistor is also connected between the RF output node and the supply voltage node, the first resistor being in parallel with the inductor.
According to the claimed invention, the resistance of the first resistor is selected such that a ratio of the inductance of the inductor to the resistance of the first resistor results in a resonant frequency seen at the RF output being greater than 1.5 times a predetermined operating frequency.
According to the claimed invention, a source of a transistor in the current mirror, the first ground node, and a capacitor are each connected to ground through three separate ground paths each having a parasitic inductance. And further, the first and second transistors, the inductor, and the first resistor can be formed on a substrate by a CMOS process, the parasitic inductances of the three separate ground paths being substantially entirely provided by three separate off-chip bonding wires.
According to the claimed invention, the first and second transistors, the inductor, and the first resistor are formed on a substrate by a CMOS process, with the first and second transistors being formed in a single deep N-well.
It is an advantage of the claimed invention that the first resistor allows the bandwidth of the LNA to be increased and the operating range to be flattened.
It is a further advantage of the claimed invention that three separate grounding paths for the source of the transistor in the current mirror, the first ground node, and the capacitor provide improved isolation and stability, and reduced noise.
It is a further advantage of the claimed invention that off-chip bonding wires provide the proper parasitic inductances to the components of the LNA, eliminating the need for specialized on chip inductors.
It is a further advantage of the claimed invention that noise is reduced by forming the first and second transistors in a single deep N-well of a CMOS circuit.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
REFERENCES:
patent: 6363127 (2002-03-01), Heinonen
patent: 6392490 (2002-05-01), Gramegna et al.
patent: 6392492 (2002-05-01), Yuan
patent: 6574292 (2003-06-01), Heinonen
patent: 2002/0090042 (2002-07-01), Heinonen
patent: 2004/0041215 (2004-03-01), Chaine et al.
Chiu Chinq-Shiun
Lin Ying-Hsi
Hsu Winston
Mottola Steven J.
Realtek Semiconductor Corp.
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