Low loss substrate for integrated passive devices

Details Low loss substrate for integrated passive devices Low loss substrate for integrated passive devices

2008-12-04

2011-12-06

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257S368000, C257S379000, C438S430000

Reexamination Certificate

active

08071461

ABSTRACT:
Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36′) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65′, 65″) in the composite dielectric region (62, 62′, 62″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in the composite dielectric region (62, 62′, 62″). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).

REFERENCES:
patent: 4139442 (1979-02-01), Bondur et al.
patent: 5190889 (1993-03-01), Poon et al.
patent: 5217919 (1993-06-01), Gaul et al.
patent: 5504033 (1996-04-01), Bajor et al.
patent: 5933746 (1999-08-01), Begley et al.
patent: 6271100 (2001-08-01), Ballantine et al.
patent: 6790751 (2004-09-01), Tsuruta et al.
patent: 7087925 (2006-08-01), Grivna
patent: 7250669 (2007-07-01), Chan et al.
patent: 7276425 (2007-10-01), Averett et al.
patent: 7326625 (2008-02-01), Jeong et al.
patent: 2003/0062588 (2003-04-01), Grivna

Affiliated with

Also associated with

Rating

Low loss substrate for integrated passive devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low loss substrate for integrated passive devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low loss substrate for integrated passive devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4265499