Low loss integrated circuit with reduced clock swing

Details Low loss integrated circuit with reduced clock swing Low loss integrated circuit with reduced clock swing

1996-09-24

1998-12-29

Tokar, Michael J.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

327544, 326 95, 326 83, H03K 17687, H03K 19096, H03K 19094, G05F 110

Patent

active

058545670

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates generally to a clock circuit for an integrated circuit which reduces power consumption.
2. Description of the Related Art
The reduction of the dissipated power becomes more and more important due to the constantly increasing complexity of VLSI circuits, on the one hand, and the greater and greater employment of such components in battery-operated mobile devices and systems as well. Particularly in integrated CMOS circuits with many registers, a considerable part of the dissipated power devolves onto the recharging of the capacitance of the clock node or, in systems with distributed clocks, the clock nodes. Between 30 and 50 percent of the overall dissipated power thereby often arises in the clock system.
The overall capacitance of the clock node is composed of the gate capacitances of the transistors connected to the clock nodes and of the wiring capacitances of the clock lines. The two components cannot simply be arbitrarily reduced. Even increasingly smaller structures as a result of technological progress do not solve this problem since the lateral dimensions of a gate and of a line are in fact reduced, but the insulation layer also becomes thinner at the same time, and the smaller lateral dimensions are used for accommodating even more functions on a given chip area. Added thereto is that, given metal tracks with a width on the order of magnitude of 1 .mu.m, the capacitance already dominates due to the edge capacitance and the coupling capacitance and is thus defined nearly only by the length of the line. A reduction of the track width leaves the edge capacitance nearly unmodified and does not significantly reduce the overall capacitance; a reduction of the interconnect spacing increases the coupling capacitance and, thus, the overall capacitance as well.
Given the fundamental assumption that the data throughput rate of the system should remain unaltered, a reduction of the switching frequency requires an increased complexity (parallelization), so that no saving of dissipated power can be achieved overall.
Another possibility of reducing the dissipated power is comprised in lowering the supply voltage of the overall circuit, whereby the supply voltage even enters quadratically into the dissipated power but requires a loss-affected matching to other circuit parts and potentially causes a reduction of the immunity to interference.
The publication PATENT ABSTRACT OF JAPAN, Volume 14, No.346 (Development discloses an output buffer circuit whereby further transistors for limiting the output amplitude are connected in series between the supply voltage terminals (VDD, VSS) and the respective output transistors, and the occurrence of malfunctions is avoided in this way.
The publication International Patent Application WO-A-92 009 141 discloses a differential output buffer circuit whose two branches are respectively wired with terminals of the full supply voltage (VDD, VSS), and the branches respectively comprise a series circuit of output transistors and an additional MOS limiting transistor, whereby the gates of the MOS limiting transistors are driven with a voltage generated in a bias generator that is lower than the full supply voltage.


SUMMARY OF THE INVENTION

An object underlying the invention is to provide an integrated circuit that has an optimally good relationship between the reduction of the overall dissipated power and the reduction of the performance capability and immunity to interference connected therewith. This and other object is inventively achieved by an integrated circuit arrangement having a clock driver circuit, a first terminal of at least a last stage of the clock driver circuit being supplied with a clock supply voltage that is lower in terms of amount than a general supply voltage of the integrated circuit, whereby a second terminal of the at least one last stage of the clock driver circuit is directly connected to reference potential, and whereby a load current flows between the first and second t

REFERENCES:
patent: 5198699 (1993-03-01), Hashimoto et al.
patent: 5355033 (1994-10-01), Jang
patent: 5436585 (1995-07-01), DiMarco
patent: 5450356 (1995-09-01), Miller

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