1988-09-30
1989-09-12
James, Andrew J.
357 239, 357 41, 357 55, 357 56, 357 67, 357 71, H01L 2978, H01L 2702, H01L 2906
Patent
active
048664928
ABSTRACT:
An improved FET is described in which a conductive layer connects the source structure to a truncated source extension which underlies an insulative gate layer and connects to a channel region. The conductive layer is of substantially lower resistivity than the source extension, thereby significantly reducing the lateral resistance of the device to diminish losses and reduce the likelihood of a parasitic bipolar transistor turning on. The invention can be implemented in both vertical and lateral devices. For a lateral device the drain is connected by a low resistance conductive layer to the gate region in a manner similar to the source.
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Intersil Corp. POWER MOS Catalog, 1981, pp. 49-59.
James Andrew J.
Ngo Ngan V.
Polyfet RF Devices, Inc.
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