Low loss capacitor structure

Details Low loss capacitor structure Low loss capacitor structure

1997-12-30

2001-01-23

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S532000, C257S535000, C257S536000, C257S537000, C257S538000, C257S748000, C257S754000, C257S920000, C257S249000, C257S296000, C257S298000, C257S300000, C257S306000

Reexamination Certificate

active

06177716

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to capacitor structures, and, more particularly, to capacitor structures for semiconductor devices and integrated circuits.
2. Relevant Background
High frequency and radio frequency (RF) systems and devices play an increasingly important role in data storage and data communication. These systems use high frequency and RF integrated circuits (ICs) that must switch signals and power at relatively high frequencies. The present invention has great utility in radio frequency switching circuits, however, the term “RF” is used herein to refer to systems, devices, and device structures that operate at high frequencies (i.e., greater than about 10 kilohertz) which includes some frequencies below and above what is conventionally described as radio frequency.
Circuits that process RF signals must provide impedance transformation from the typically low terminal impedance of transistors to different impedance antennas or other active devices. Impedance transformation may be accomplished using inductor-capacitor transformation networks. RF ICs require low loss inductors and capacitors to function efficiently. Lossy inductors and capacitors dissipate energy as heat that must be removed from the IC package. Heat removal limits device performance and functionality and makes the IC larger and thus more expensive, as well as making the packaging more expensive.
As a result of the low Q components available in existing integrated circuit structures, impedance transformation ability of monolithic integrated circuits is limited. Losses in capacitors and inductors limit the impedance transformation of each transformation network stage. The transformation Q cannot exceed the loaded Q without the losses becoming excessive. The transformation Q is often referred to as the loaded Q or Q
l
. The unloaded Q (i.e., Q
u
) represents the component losses.
A typical input impedance' for a two watt power MOSFET at 900 MHz is (4-21.4j) ohms. This input impedance needs to be transformed to approximately 20.2 Ohms which is the load required by a preceding stage driving the MOSFET. A single L-section with an inductor Q of 5 will cause a 3 dB insertion loss.
Attempts have been made to improve the system Q by improving the inductor Q. Microstrip inductors can have the metallization series resistance decreased by connecting additional layers of metal. The loss limiting mechanism for transformation networks soon becomes the parasitic capacitor coupling into the low resistance substrate. This limits the practical Q to a range of about 5 to 10 for monolithic inductive elements. The Q can be raised by decreasing the parasitic capacitance of the inductor with additional layers of dielectric, which adds cost and lowers yields. Hence, improvement of the capacitor Q is a desirable way to improve overall Q of the transformation network.
In the past, the low per-stage impedance transformation ability was addressed by using a greater number of impedance transformation stages. However, a greater number of impedance transformation stages increases the number of components and the size of the integrated circuit. Because fewer integrated circuits can be placed on a single wafer or substrate, the integrated circuit cost increases. By reducing the losses in the capacitor circuits of an integrated circuit, the number of active stages required decreases and the space efficiency of the overall layout increases. Efficiency of RF power amplifiers is a major advantage in the cellular and personal communication systems marketplace.
In addition to high Q, integrated capacitors are desirably volumetrically efficient. In other words, the capacitor structure should have a high capacitance per unit volume ratio. One prior method of increasing the capacitance per unit volume in an integrated circuit is to use thinner capacitor dielectric layers between the capacitor plates. Capacitor plates can be spaced closely together using thin film conductors such as polycrystalline silicon (e.g., polysilicon, doped polysilicon, and polysilicon silicide) separated by thin film dielectrics such as silicon dioxide. However, conductors such as polysilicon silicide, also called “polycide”, have high sheet resistance as compared to metals in the range of four Ohms per square and thus increase the RC time constant for a capacitor element.
Conductor plates comprising materials with lower resistivities such as metals, which are desirable from a high Q standpoint, are not compatible with the temperatures and processes involved to form the thin dielectric layers in an integrated circuit. With low resistivity metal capacitor plates, the relatively thick capacitor dielectrics severely reduce capacitance per unit area for an integrated circuit. It is advantageous to provide an integrated circuit construction method and structure that provide low loss, compact capacitors capable of being monolithically integrated in radio frequency power amplifiers.
Another prior method for improving capacitance density is to provide a capacitor structure comprising lossy plates having a high resistivity material surrounded by low resistivity material at the periphery. For small area capacitors, this type of structure works well but the reduction in resistance diminishes quickly for larger capacitor structures. For example, if a rectangular capacitor structure is extended in one direction beyond one square, the resistance does not drop appreciably. If the rectangular capacitor is extended in the opposite direction, the resistance will drop, but the form factor of the capacitor is poor making it more difficult to integrate with other components. What is needed is a capacitor structure with a highly adaptable form factor yet providing low resistance and high capacitance per unit volume for large capacitor structures.
SUMMARY OF THE INVENTION
Briefly stated, the present invention involves a capacitor structure including first and second capacitor plates insulatingly spaced from each other by a capacitor dielectric. A first set of conductive posts electrically couple to the first capacitor plate and extend away from the capacitor dielectric. A first conductive structure comprising a material with lower resistivity than the first capacitor plate is electrically coupled to the first set of conductive posts. In a preferred embodiment, a second set of conductive posts are electrically coupled to the second capacitor plate and extend away from the capacitor dielectric. A second conductive structure is electrically coupled to the second set of conductive posts. The first and second conductive structures provide low resistance contacts to the capacitor.
In another aspect, the present invention involves a method for forming a capacitor on a supporting substrate by forming a first capacitor plate on the substrate. A capacitor dielectric is formed over the first capacitor plate with a second capacitor plate formed over the first capacitor plate and separated from the first capacitor plate by the capacitor dielectric. The second capacitor plate is covered by a first dielectric. A first set of vias is formed in the first dielectric that extend through the second capacitor plate to expose portions of the first capacitor plate. Each of the first set of vias is filled with conductive posts that electrically couple to the first capacitor plate. A patterned metallization is provided to electrically couple the conductive posts to form a low resistivity coupling to the first capacitor plate. In a preferred embodiment, the patterned metallization is covered with a second dielectric and a second set of vias is formed through the second dielectric to expose portions of the second capacitor plate. Each of the second set of vias is filled with conductive posts extending through the second dielectric and electrically coupling to the second capacitor plate. A patterned metallization electrically coupling the conductive posts in the second dielectric is provided to form a low resistivity coupling to the second capacit

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