Low lock time delay locked loops using time cycle suppressor

Details Low lock time delay locked loops using time cycle suppressor Low lock time delay locked loops using time cycle suppressor

2007-08-14

2007-08-14

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S299000

Reexamination Certificate

active

10538375

ABSTRACT:
The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.

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