Low level input voltage comparator

Details Low level input voltage comparator Low level input voltage comparator

1999-11-19

2001-03-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

Reexamination Certificate

active

06198312

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to circuits and more particularly to a voltage comparator circuit.
BACKGROUND ART
Voltage comparators are useful circuit blocks that can be implemented to operate in a wide variety of applications. For example, voltage comparators may be utilized to detect zero crossings of an arbitrary signal waveform. As another example, voltage comparators may be utilized to convert sine waves into square waves. Voltage comparators can also be used in current sensing applications by monitoring the voltage at a specified node of a circuit.
A block diagram of a conventional voltage comparator
10
is shown in FIG.
1
. The voltage comparator includes inputs
12
and
14
and an output
16
. The input
12
is configured to receive an input voltage V
i
, while the input
14
is configured to receive a reference voltage V
r
. The reference voltage V
r
constitutes the comparator threshold. In operation, if the input voltage V
i
is greater than the reference voltage V
r
, the voltage comparator provides a high level signal V
o+
on the output. Alternatively, if the input voltage V
i
is less than the reference voltage, the voltage comparator provides a low level signal V
o−
on the output.
The transfer characteristics of the voltage comparator
10
are illustrated in FIG.
2
. The plot
18
of
FIG. 2
is the voltage on the output
16
of the voltage comparator with changes to the input voltage V
i
When V
i
<V
r
, the voltage on the output is the low level signal V
o−
. However, when V
i>V
r
, the voltage on the output is the high level signal V
o+
. For a zero crossing detection application, the reference voltage V
r
equals zero voltage. In other applications, however, the reference voltages can be other than zero voltage. For a wave conversion application, the high level signal V
o+
and the low level signal V
o−
are selectively set to produce the desired square wave.
Conventional voltage comparators, as illustrated by the voltage comparator
10
of
FIG. 1
, may operate well for their intended purposes. However, when the input voltage to be compared is very close to the reference voltage (e.g., supply voltage or the electrical ground), these conventional voltage comparators may not function as designed. In light of this concern, what is needed is a voltage comparator that can operate properly even when the input voltage is in the order of millivolts with respect to the reference voltage, such as the supply voltage or the electrical ground.
SUMMARY OF THE INVENTION
A circuit and a method for comparing an input voltage to an internally generated reference voltage utilize a bias network to make the voltage comparison. The bias network is preferably configured to generate a proportional-to-absolute-temperature (PTAT) reference voltage, which is used for the voltage comparison. Although the circuit can be implemented to operate in a number of applications, the circuit is particularly useful in a current sensing application. The circuit can be configured to accurately sense voltages near the supply voltage or the electrical ground.
In a first embodiment, the circuit is configured to sense input voltages that are near the supply voltage. The circuit includes the bias network and a comparison current path. The bias network includes a resistor, a first p-type metal-oxide semiconductor (PMOS) transistor and a first n-type metal-oxide semiconductor (NMOS) transistor that are connected in series between a high voltage terminal and a low voltage terminal to form a first current path. The bias network also includes a second PMOS transistor and a second NMOS transistor that are connected in series between the high voltage terminal and the low voltage terminal to form a second current path. The high voltage terminal may provide the supply voltage. The low voltage terminal may be grounded.
In this embodiment, the NMOS transistors of the bias network are of the same size and connected as a current mirror to source the same current level to the PMOS transistors of the bias network. However, the size of the first PMOS transistor on the first current path is M times the size of the second PMOS transistor on the second current path. In a preferred embodiment, the resistor on the first current path provides sufficient electrical resistance so that the PMOS transistors operate in a sub-threshold region to generate the PTAT reference voltage. The reference voltage is generated on the first current path of the bias network, such that the voltage on the source of the first PMOS is the reference voltage.
The comparison current path of the circuit includes a third PMOS transistor and a third NMOS transistor that are connected in series between an input voltage terminal and the low voltage terminal. The sizes of the third PMOS transistor and the third NMOS transistors of the comparison current path are same as the sizes of the first PMOS transistor and the first NMOS transistors, respectively, on the first current path of the bias network. The gate of the third PMOS transistor is coupled to the gate of the first PMOS transistor, while the gate of the third NMOS transistor is coupled to the gate of the first NMOS transistor. An output terminal is connected to the comparison current path between the third PMOS transistor and the third NMOS transistor. The output terminal provides a comparison signal that is indicative of the comparison of the input voltage to the reference voltage.
When the input voltage applied to the input voltage terminal of the comparison current path is equivalent to the generated reference voltage, the conditions on the third PMOS transistor and the third NMOS transistor of the comparison current path are equivalent to the conditions on the first PMOS transistor and the first NMOS transistor of the first current path of the bias network with respect to currents and voltages. However, if the input voltage is greater than the reference voltage, the v
gs
of the third PMOS transistor is greater than the v
gs
of the first PMOS transistor, which results in a high signal on the output terminal. Conversely, if the input voltage is less than the reference voltage, the v
gs
of the third PMOS transistor is less than the v
gs
of the first PMOS transistor, which results in a low signal on the output terminal. Thus, the third PMOS transistor functions as an active device to drive the output terminal, either high or low, in response to the input voltage.
In a second embodiment, the circuit is configured to sense input voltages that are near the electrical ground. In this embodiment, the comparison circuit is connected between the high voltage terminal and the input voltage terminal. In addition, the PMOS transistors of the bias network are of the same size and are configured as a current mirror to source the same amount of current to the NMOS transistors of the bias network, while the NMOS transistors of the bias network have sizes that are proportional to each other. Consequently, the NMOS transistor on the second current path of the comparison current path functions as the active device to drive the output terminal, either high or low, in response to the input voltage.
In either embodiments, the circuit requires a startup circuit to initiate the bias network to conduct current through the first and second current paths. In effect, the startup circuit changes the operating state of the bias network from a non-conducting stable state to a conducting stable state. An exemplary startup circuit for the first embodiment includes a start transistor that is coupled to the NMOS transistors of the bias network that are functioning as a current mirror. The activation of the start transistor turns on the NMOS transistors of the bias network to a conducting state, thereby allowing current to conduct through the first and second current path of the bias network. The exemplary startup circuit also includes a shut-off transistor that is connected to the first current path of the bias network. The shut-off transistor operates to deactivat

Affiliated with

Also associated with

Rating

Low level input voltage comparator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low level input voltage comparator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low level input voltage comparator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2539589