Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-08-16
2003-04-08
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
Reexamination Certificate
active
06545512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to dynamic logic circuits, and more particularly to dynamic logic circuits having circuitry for a reduced power consumption state.
2. Related Art
Due to its speed, it is well known to use dynamic circuitry for high-performance applications.
FIG. 1
illustrates a prototypical prior art dynamic logic circuit
100
. The circuit
100
has a dynamic node
150
which is precharged to a high voltage during a precharge phase timed by clock
115
. Then during an evaluation phase, also timed by clock
115
, the dynamic node
150
may be selectively pulled down to a low voltage through input circuitry
122
, depending on the state of the inputs.
More specifically, during the phase of clock
115
when the clock signal is low, PFET
101
in timing circuitry
120
is turned on and NFET
108
is turned off, which pulls dynamic node
150
up to Vdd. Then during the evaluation phase, that is, during the phase of clock
115
when the clock signal is high, PFET
101
is turned off and NFET
108
is turned on, so that the dynamic node
150
may be selectively pulled down to a low voltage through the NFET's
110
through
107
of input circuitry
122
, depending on the state of the inputs on the gates
110
through
113
.
The dynamic circuit
100
of
FIG. 1
is a “domino” type of dynamic circuit, which includes an output stage, output circuitry
124
, that enables chaining a number of dynamic circuits in series, or series-parallel combinations. That is, output circuitry
124
is a static gate which converts the state of the dynamic node
150
so that when the dynamic node
150
is in the precharged state the output signal on node
114
is low. Thus, even if the foot FET
108
is omitted in the next stage, the output
114
may be an input to a next dynamic logic circuit in a series without interfering in the pre charging of the dynamic node in the next dynamic logic circuit.
The dynamic circuit
100
also has keeper circuitry
126
coupled to the output
114
, Vdd, and the dynamic node
150
for keeping the dynamic node at the precharged state during the evaluation phase despite leakage through the input circuitry
122
and the foot device
108
if none of the inputs are active.
It is known in low power consumption applications to have a “sleep” mode during which the logic circuitry is nonfunctional, or at least has a reduced functionality, and has reduced power consumption. Conventionally, dynamic logic circuits have not been as widely used as have static logic circuits in applications requiring low-power consumption. However, there is a current trend requiring higher performance for embedded processors in applications such as personal digital assistants, cell phones, electronic books, watches, etc. This is particularly brought on by the demand for rendering of images by such devices, such as for Internet browsers. The embedded processors in these applications are frequently battery powered, so there is an increasing need for reduced power consumption in dynamic logic circuits.
SUMMARY OF THE INVENTION
The foregoing need is addressed in the present invention, according to which a dynamic circuit includes a sleep mode cutoff transistor coupled to an inverter stage to minimize power consumption.
More particularly, the dynamic circuit includes a dynamic node and precharge timing circuitry. The precharge timing circuitry is coupled to the dynamic node and a voltage source for driving the dynamic node to a operating voltage state during a precharge interval responsive to a precharge signal. The dynamic circuit further includes input circuitry coupled to the dynamic node for selectively pulling the dynamic node to a low voltage state during an evaluation interval responsive to one or more input signals, and output circuitry coupled to the dynamic node and to an output node for inverting the dynamic node voltage. Also, sleep circuitry coupled to the output circuitry is operable to isolate the output node from ground during a sleep interval responsive to a sleep signal. It is an object of the invention for power consumption of the circuitry to be reduced in the sleep mode. The circuitry may use somewhat more power in the sleep mode than it does if power to the circuitry is merely turned off, but if power to the circuitry is turned off the circuitry has indeterminate voltage states. Therefore, the sleep mode is advantageous because in the sleep mode the circuitry uses less power than in normal operation and the circuitry has a determinate state.
In a further aspect, during the sleep interval, in which the sleep circuitry isolates the output node from ground responsive to the sleep signal, the circuitry is operable to pull the dynamic node signal to ground and drive the output signal to the operating voltage state.
In a still further aspect, the precharge signal drives to a voltage level above that of the operating voltage during the sleep interval, so that leakage current through the precharge timing circuitry is reduced during the sleep interval. That is, in an embodiment the gate voltage of a PFET in a leakage path is driven to the higher voltage level, turning the PFET off more fully.
In yet another aspect, the sleep signal goes to a voltage level below ground during the sleep interval, so that leakage current through the output circuitry is reduced during the sleep interval. That is, in an embodiment the gate voltage of an NFET in a leakage path is driven to the lower voltage level, turning the NFET off more fully.
Not all of the transistors in a leakage path are necessarily driven more fully off. For example, a keeper PFET provides a leakage path, but in an embodiment this transistor's gate is not driven above the operating voltage for the sleep because the keeper PFET is a relatively small device, much smaller than the pre charge PFET, so it's leakage is considerably less.
Further, in an alternative, the circuitry includes evaluation timing circuitry interposed between the input circuitry and ground for controlling timing of the evaluation interval responsive to an evaluation signal.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
REFERENCES:
patent: 5841304 (1998-11-01), Tam
patent: 5900759 (1999-05-01), Tam
patent: 6121796 (2000-09-01), Ciraula et al.
patent: 6377080 (2002-04-01), Arnold
patent: 6404235 (2002-06-01), Nowka et al.
England Anthony V. S.
International Business Machines - Corporation
Salys Casimer K.
Zweizig Jeffrey
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