Low leakage power transistor and method of forming

Details Low leakage power transistor and method of forming Low leakage power transistor and method of forming

2005-06-21

2005-06-21

Flynn, Nathan J. (Department: 2826)

Semiconductor device manufacturing: process

Chemical etching

C438S527000, C438S228000, C438S247000, C438S252000, C438S224000, C438S687000, C438S688000

Reexamination Certificate

active

06908859

ABSTRACT:
A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.

REFERENCES:
patent: 4260431 (1981-04-01), Piotrowski
patent: 5132235 (1992-07-01), Williams et al.
patent: 6211003 (2001-04-01), Taniguchi et al.
patent: 6413810 (2002-07-01), Matsuhashi
patent: 2002/0185673 (2002-12-01), Hsu et al.
patent: 2002/0197779 (2002-12-01), Evans
patent: 2003/0003660 (2003-01-01), Hsu et al.
Power BICMOS Process with High Voltage Device Implementation for 20V Mixed Signal Circuit Applications, Nehrer et al., Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs, Osaka, pp. 263-266.

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