Low leakage PMOS on-chip decoupling capacitor cells...

Details Low leakage PMOS on-chip decoupling capacitor cells... Low leakage PMOS on-chip decoupling capacitor cells...

2002-06-04

2003-08-19

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S069000, C257S204000, C257S338000, C257S357000, C257S371000, C257S516000, C257S528000, C438S199000, C438S210000, C438S329000

Reexamination Certificate

active

06608365

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to on-chip decoupling capacitors that are used with CMOS integrated circuits.
BACKGROUND OF THE INVENTION
Power supply noise, simultaneous switching noise, or dynamic switching noise, is one of the most significant noise problems in deep sub-micron integrated circuits. The problem stems from switching noise on the power supply lines that are coupled onto the signal nodes of the circuits. One method for reducing the power supply noise is to scale down the core power supply voltage, such as from 1.8 volts to 1.2 volts, for instance.
The most effective way to reduce power supply noise, however, is to increase on-chip decoupling capacitance. This is typically done in a CMOS (complementary MOS) circuit, for example, by locating on-chip decoupling capacitors next to the standard CMOS cells comprising the circuit.
CMOS is the most widely used type of integrated circuit for digital processors and memories. CMOS uses both p- and n-type MOS (PMOS and NMOS) transistors wired together in its circuits that cause less power to be used than PMOS-only or NMOS-only circuits.
FIGS. 1A and 1B
are diagrams illustrating a conventional CMOS decoupling capacitor cell.
FIG. 1A
is a top view of the CMOS decoupling capacitor cell, and
FIG. 1B
is a cross-sectional view of the cell. The CMOS decoupling capacitor cell
10
includes a PMOS transistor
12
and an NMOS transistor
14
, which are connected between VDD and VSS metal rails
16
and
18
. Both transistors
12
and
14
used a thin gate oxide
20
to form the decoupling capacitor. The PMOS transistor
12
includes p-islands
22
formed within and an n-well
24
, while the NMOS transistor
14
includes n-islands
26
formed within a p-well
28
.
CMOS decoupling capacitor cells
10
are typically located side-by-side with standard CMOS cells (not shown). The n-wells
24
of the PMOS transistors
12
of adjacent cells are aligned to form a row and to thereby achieve higher cell densities. Each CMOS decoupling capacitor cell
10
is separated from the adjacent CMOS cells by a cell boundary
30
, which also defines the area for the cell
10
.
One requirement for a CMOS decoupling capacitor cell
10
is that it be highly efficient, meaning that its unit area should produce the maximum capacitance with minimal leakage. While conventional CMOS decoupling capacitors cells
10
achieve high capacitance, the NMOS transistor
14
produces a high rate of leakage, due mainly to the nature of the thin gate oxide
30
. For example, if a capacitance per cell of 70 nf is required, the leakage current for CMOS decoupling capacitors
10
can be as high as 0.14 mA. Therefore, the leakage per unit capacitance of conventional CMOS decoupling capacitor cells
10
is not optimized.
It has been observed on that in the inversion region, gate leakage for the PMOS transistor
12
is about ten times lower than the for the NMOS transistor
14
. Consequently, on-chip decoupling capacitors have been produced that have a single PMOS transistor
12
to improve leakage. However, because the area typically occupied by the NMOS transistor
14
is unused, PMOS decoupling capacitor cells have the disadvantage of having lower capacitance per area than CMOS decoupling capacitor cells
10
.
Accordingly, what is needed is an on-chip decoupling capacitor cell having reduced leakage, but that maintains capacitance per area and compatibility with standard CMOS cells. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides an on-chip decoupling capacitor cell that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area. In one embodiment, the n-well and the n-well extension from a single T-shaped n-well for the PMOS transistor.
According to the present invention, a super capacitance decoupling capacitor (SCAP) cell is provided that has reduced leakage compared with traditional CMOS capacitor cells and greater capacitance per unit area than traditional PMOS capacitor cells.


REFERENCES:
patent: 6144076 (2000-11-01), Puchner et al.
patent: 6541840 (2003-04-01), Terayama et al.

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