Low leakage N-channel SOS transistors and method of making them

Metal treatment – Compositions – Heat treating

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148175, 357 23, 357 42, 357 50, 357 91, H01L 21265, H01L 1100

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042525748

ABSTRACT:
A method for making low leakage N-channel silicon-on-sapphire (SOS) transistor is described. The transistor has reduced edge leakage as a result of acceptor ion impurities introduced into the edges of the silicon islands on which the transistor is formed. The acceptor impurities are introduced into the epitaxial silicon layer immediately before etching the layer to produce the islands. The impurities are then diffused under the edge of the masking layer prior to the removal of the portions of the silicon epitaxial layer, and leaving the edges of the islands more heavily doped than the surface of the island.

REFERENCES:
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patent: 3890632 (1975-06-01), Ham et al.
patent: 3933529 (1976-01-01), Goser
patent: 4002501 (1977-01-01), Tamura
patent: 4070211 (1978-01-01), Harari
patent: 4097314 (1978-06-01), Schlesier et al.
patent: 4104087 (1978-08-01), Ipri et al.
patent: 4178191 (1979-12-01), Flatley
patent: 4179792 (1979-12-01), Marshall et al.
Ipri et al., IEEE-Trans. Electron Devices, (Sep. 1976), pp. 1110-1112.
McGreivy, D. J. IEEE-Trans. Electron Devices, ED-24, (1977), 730.

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