Low leakage ESD network for protecting semiconductor devices and

Details Low leakage ESD network for protecting semiconductor devices and Low leakage ESD network for protecting semiconductor devices and

1995-02-27

1996-10-08

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, 361118, H02H 900

Patent

active

055637574

ABSTRACT:
A low leakage ESD network (24) is provided for protecting a semiconductor device (22). The ESD network (24) comprises an ESD circuit (28) and a bias circuit (30). The ESD circuit (28) is connected to an input of the semiconductor device (22). The ESD circuit (28) is operable to protect the input of the semiconductor device (22) against electro-static discharge. The bias circuit (30) is connected to the input of the semiconductor device (22) and to the ESD circuit (28). The bias circuit (30) is operable to actively bias the ESD circuit (28) such that a voltage difference across each current leakage path in the ESD circuit (28) is held substantially equal to zero volts during normal operation of the semiconductor device (22).

REFERENCES:
patent: 4158863 (1979-06-01), Naylor
patent: 4694277 (1987-09-01), Takahashi
patent: 5416030 (1995-05-01), Elkind et al.

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