Low-leakage DRAM structures using selective silicon...

Details Low-leakage DRAM structures using selective silicon... Low-leakage DRAM structures using selective silicon...

2001-09-27

2002-05-07

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S296000, C257S304000, C438S705000, C438S253000

Reexamination Certificate

active

06384437

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for fabricating Dynamic Random Access Memory (DRAM) cells using selective silicon epitaxial growth over an insulating layer on the cell (device) areas. The method is particularly useful for reducing capacitor leakage currents and soft error due to Alpha particles on DRAM cells.
(2) Description of the Prior Art
Advances in the semiconductor process technologies have dramatically decreased the semiconductor device feature sizes and increased the circuit density on the integrated circuits on chips. One device type that has experienced a rapid increase in density is the array of memory cells on DRAM devices. Each memory cell consists of a single pass transistor (FET) and a storage capacitor. As the cell area decreases and the capacitance of the storage capacitor decreases, it becomes increasingly difficult to maintain sufficient charge on the capacitor due to the capacitor leakage current, and the refresh cycle time needed to maintain the charge on the capacitor becomes unacceptably short. Another problem is the natural presence of Alpha particles, which can generate electron-hole pairs resulting in soft errors in the more conventional DRAM capacitors in which their node contacts are made directly to the diffused junctions in the silicon substrate.
One method of reducing the leakage current and reducing soft error is to use a silicon-on-insulator (SOI). However, SOI technology is still too expensive and complicated for manufacturing. However, as devices are further diminished in size, the junction depths and well depths decrease proportionally. The use of a thin silicon epitaxial layer is required for future device generations to achieve these shallow device structures.
Several methods for making and using SOI have been described in the literature. For example, in U.S. Pat. No. 5,691,776 to Hebert et al. a method is described for forming field oxide regions by etching trenches in which a conformal silicon nitride (Si
3
N
4
) is deposited over the trenches. An opening is etched in the Si
3
N
4
layer and a selective epitaxial growth (SEG) is used to partially fill the trenches. The SEG is then thermally oxidized to form the field oxide. In U.S. Pat. No. 5,686,343 to Lee, Lee isolates a semiconductor layer on an insulator by first forming an insulating layer on a silicon substrate, etching a window to the substrate, depositing an amorphous silicon layer that is annealed to form an epitaxial layer over the window. The epitaxial layer is patterned and a Si
3
N
4
layer is deposited over the patterned epitaxial layer, and a thermal oxidation is used to oxidize the silicon in the window under the semiconductor layer. In U.S. Pat. No. 6,037,199 to Huang et al. an insulating layer is formed on a silicon substrate, an opening is formed in the insulator, and an amorphous silicon layer is deposited and annealed to form an epitaxial layer extending from the opening laterally over the insulating layer. The epitaxial layer is patterned over the insulating layer to form isolated silicon regions (islands) in which FETs are formed. In U.S. Pat. No. 5,763,314 to Chittipeddi a method is described for forming two separate selective epitaxial layers, having different dopant concentrations, on the same silicon substrate. The epitaxial layers are separated by a trench filled with an insulating material.
However, there is still a strong need in the semiconductor industry to provide DRAM cells with low capacitor-leakage currents and reduced Alpha soft errors while providing a process that is integratable into the current manufacturing process without significantly increasing manufacturing process complexity.
SUMMARY OF THE INVENTION
Therefore a principal object of this invention is to make DRAM cells with increased cell density while reducing capacitor leakage currents.
Another object of this invention is to reduce the leakage currents and soft error by using a silicon epitaxial layer over an insulating layer on which are formed the DRAM FETs and storage capacitors.
It is another object to integrate this novel DRAM cell into the current DRAM process to minimize manufacturing cost by integrating the selective silicon epitaxy on insulator without significantly increasing the processing steps.
Another objective of this invention by a first embodiment is to make a flat capacitor structure using this selective epitaxy DRAM process having low leakage currents.
Still another objective of this invention by a second embodiment is to make a stacked capacitor structure using this selective epitaxy DRAM process having low leakage currents.
In accordance with the objects of the present invention a method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate is described. The method by a first embodiment begins by providing a P doped single-crystal silicon semiconductor substrate for N channel FETs. Alternatively an N doped substrate can be used if P channel FETs are desired. A first insulating layer that also serves as a stress-release layer is formed on the substrate. A hard-mask layer composed of Si
3
N
4
is deposited on the first insulating layer. The hard mask is patterned to leave portions over the desired device areas. The hard mask and plasma etching are then used to etch shallow trenches in the substrate that are aligned to the hard mask (cell or device areas). A second insulating layer is deposited to a thickness sufficient to fill the shallow trenches and is polished back to the hard-mask layer to form shallow trench isolation and to expose the hard-mask surface. The hard-mask layer is selectively removed, such as by wet etching in a hot phosphoric acid solution. This results in recesses in the field oxide isolation that are self-aligned over the device areas and also exposes the first insulating (stress-release) layer in the recesses. Next, openings are etched in the first insulating layer over the device areas to expose the substrate. For example, the bit line contact mask can be used to etch the openings, thereby saving additional mask cost. Next, an epitaxial layer is selectively grown from the silicon substrate exposed in the openings and extends laterally over the first insulating layer in the recesses. By the method of a first embodiment, a portion of the epitaxial layer is doped N
+
over the first insulating layer to form capacitor bottom electrodes in regions where flat capacitors are to be formed for the DRAM cells. A thin gate oxide is formed on the epitaxial layer, for example by thermal oxidation. A polysilicon layer is deposited on the substrate and is doped N
+
by ion implantation. The polysilicon layer is then patterned to form FET gate electrodes over the openings in the first insulating layer and also to form capacitor top electrodes for the capacitors over the capacitor bottom electrodes. The FET thin gate oxide also serves as an interelectrode dielectric layer for the flat capacitor. In addition, the polysilicon layer can be concurrently patterned to form polysilicon resistors on the shallow trench isolation. Lightly doped source/drain areas are formed in the epitaxial layer adjacent to the gate electrodes, and insulating sidewall spacers are then formed on the gate electrodes. The DRAM FETs are now completed by forming first and second source/drain contact areas, one on each side of the FET gate electrode adjacent to the sidewall spacers, by ion implantation. The dopant regions in the first source/drain contact areas are contiguous with the doped capacitor bottom electrodes. Bit line electrical contacts are formed to the second source/drain areas to complete the DRAM cells.
In the second embodiment the process is identical to the first embodiment up to and including the deposition of the polysilicon layer to form the gate electrodes. The implant to form the bottom ele

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