Low-leakage diode string for use in the power-rail ESD clamp...

Details Low-leakage diode string for use in the power-rail ESD clamp... Low-leakage diode string for use in the power-rail ESD clamp...

2000-09-11

2003-12-30

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000

Reexamination Certificate

active

06671153

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to ElectroStatic Discharge (ESD) protection for integrated circuits and more particularly to series connected diode strings employed for ESD protection.
2. Description of Related Art
1. ElectroStatic Discharge (ESD)
ElectroStatic Discharge (ESD) has been a serious reliability concern with respect to CMOS types of integrated circuit (IC) devices. As CMOS technology progresses into the deep sub-micron scale, the use of advanced processes such as thinner gate oxide, shorter channel length, shallower junction depth, LDD (Lightly-Doped Drain) structure, and salicide (Self-Aligned Silicide) diffusion is employed. The disadvantage of use of these processes on this extremely small scale is that there is serious degradation of the robustness of CMOS IC devices in avoiding of problems associated with ESD. In order to obtain suitable high robustness against damage from ESD, a CMOS IC must incorporate ESD protection circuits at every input and output pin. Nevertheless some unexpected ESD damage occurs in the internal circuits of CMOS IC devices beyond the input or output ESD protection circuits [1]-[6]. Even the parasitic capacitance and resistance along the power lines of an IC can also cause a negative impact on the ESD reliability of the CMOS IC [4]-[6].
As stress induced ESD effects may occur in response to positive or negative voltage on an input (or output) pin with respect to the grounded VDD or VSS pins, there are four different ESD stress combinations at each input (output) pin as shown in
FIGS. 1A-1D
[7]. Referring to
FIGS. 1A-1D
, a CMOS IC
10
which is housed within a dual-in-line package
12
having input/output pins
14
includes VDD pin
14
a
and VSS pin
14
b.
Since ESD voltages may have positive or negative polarities on a pad associated with the VDD or the VSS pins
14
a
,
14
b
, there are four different ESD-stress mode conditions.
FIGS. 1A-1D
show modes of test combinations for ESD stress on an input (or output) pin with respect to the grounded VDD or VSS pins.
FIG. 1A
shows the PS-mode.
FIG. 1B
shows the NS-mode.
FIG. 1C
shows the PD-mode.
FIG. 1D
shows the NS-mode. Therefore input and output ESD protection circuits are designed to bypass the ESD current from the stress pin to the VDD or VSS pins.
(1) PS mode: ESD stress at a pin
14
c
with positive voltage polarity to the grounded VSS (GND) pin
14
b
when VDD pin
14
a
and other input/output pins
14
are floating (FIG.
1
A);
(2) NS mode: ESD stress at a pin
14
c
with negative voltage polarity to the grounded VSS. (GND) pin
14
b
when VDD pin
14
a
and other input/output pins
14
are floating (FIG.
1
B).
(3) PD mode: ESD stress at a pin
14
c
with positive voltage polarity to the grounded VDD pin
14
a
when VSS (GND) pin
14
b
and other input/output pins
14
are floating (FIG.
1
C).
(4) ND mode: ESD stress at a pin
14
c
with negative voltage polarity to the grounded VDD pin
14
a
when VSS (GND) pin
14
b
and other input/output pins
14
are floating (FIG.
1
D).
For comprehensive ESD testing, additional ESD stress combinations are shown in
FIGS. 2A-2D
. These four additional ESD-testing combinations are used to verify the whole-chip ESD reliability. These additional ESD stress combinations have been specified in the ESD testing standard to verify the whole-chip ESD reliability [7].
FIGS. 2A and 2B
show the pin-to-pin ESD stress with the ESD voltage being applied to an input (or output) pin while all other input and output pins except for the VDD and VSS pins
14
a
/
14
b
are grounded.
FIGS. 2C and 2D
show the VDD-to-VSS ESD stress with the ESD voltage being directly applied to the VDD pin
14
a
with the VSS pin
14
b
grounded while all input and output pins are floating. The additional ESD testing combinations of
FIGS. 2A-2D
often lead to more complex ESD current paths from the power lines to internal circuits, which causes some unexpected damage to the internal circuits in spite of providing input and output ESD protection circuits in the IC devices [8]-[10].
FIG. 3
shows ESD current discharging paths in an IC during pin-to-pin ESD stress conditions. In particular, the pin-to-pin ESD stress, as shown in
FIG. 3
, often causes some unexpected ESD damage located in the internal circuits, rather than damaging the input or output ESD protection circuits. In
FIG. 3
, a positive ESD voltage is applied to an input pin IP with an output pin OP being grounded, while the VDD and VSS pins are both floating. The ESD current is diverted from the input pad IP to the floating VDD power line through the forward-biased diode D
2
, above diode D
1
, in the input ESD protection circuit. The ESD current flowing through the VDD power line can be diverted into the internal circuit INT through a connection to the VDD line. Then, the ESD current, which is discharged through the internal circuit INT, may cause random ESD damage in the internal circuit INT, along the Path_
1
current path shown as dotted line in FIG.
3
.
If there is an ESD clamp circuit CC, in parallel with the internal circuit INT, across the power rails comprising VDD power line and VSS ground line, the ESD current can be discharged through the Path_
2
current path shown in FIG.
3
. Therefore, the internal circuit INT can be safely protected against ESD damage. Thus, an efficient ESD clamp circuit between the power supplies is necessary to protect the internal circuit INT against ESD damage [11]-[16].
In summary, in
FIG. 3
the ESD current discharging paths are shown in an IC during a pin-to-pin ESD stress condition. If the IC has no ESD clamp circuit CC between the power rails (VDD power line and VSS ground line), the ESD current is discharged through the Path_
1
, which often causes ESD damage to the internal circuit INT. If the IC has an effective ESD clamp circuit CC between the VDD and VSS power rails, the ESD current is discharged through the Path_
2
.
2. Diode Strings
2.1. The Diode String
Because a diode in the forward-biased condition can sustain a much higher ESD level than it can in the reverse-biased condition, a diode string with multiple cascaded diodes is therefore provided to clamp the ESD overstress voltage on the 3.3 Volts/5 Volts tolerant I/O pad [12] or between the mixed-voltage power lines [13]-[15].
FIG. 4A
is a schematic circuit diagram which illustrates a PNP-based circuit
16
which incorporates a diode string D
1
, D
2
, . . . , Dn−1, Dn of diodes connected in series from power rail VDD to ground rail VSS. The circuit
16
is used as the ESD clamp from the power rail VDD to VSS power rail.
FIG. 4B
is a cross-sectional view showing a device
16
′ which is an embodiment of the circuit
16
of FIG.
4
A. Diode string D
1
, D
2
, . . . , Dn−1, Dn is formed in a P-substrate
18
with the diodes formed in N-wells in substrate
18
which contains CMOS devices, not shown for convenience of illustration.
Each diode D
1
, D
2
, . . . , Dn−1, Dn forms a parasitic vertical PNP transistor S
1
, S
2
, . . . , Sn−1, Sn with P-substrate
18
in a common collector configuration. The required number “n”, which is a positive integer, of diodes in the diode string of
FIGS. 4A and 4B
depends on three parameters, the leakage current I
Leakage
allowed at maximum operating voltage and temperature, the parasitic vertical PNP &bgr; gain, and the blocking voltage across the diode string. These relationships have been reported earlier [13]-[15]. The relevant equations are presented in the following:
V
String
⁡
(
I
)
=
mV
D
-
nV
T
×
[
m
⁡
(
m
-
1
)
2
]
×
ln
⁡
(
β
+
1
)
(
1
)
 
V
D
(
I
)=
nV
T
×(
I/AI
S
)  (2)
I
D
=AIs
(
e
V
V
T
−1)  (3)
V
D
(
T
1
)=
nE
g0
+(
T
1
/
T
0
)×(
V
D
(
T
0
)−
nE
g0
/q
)  (4)
where
V
string
=total voltage drop across m diodes,

Affiliated with

Also associated with

Rating

Low-leakage diode string for use in the power-rail ESD clamp... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-leakage diode string for use in the power-rail ESD clamp..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-leakage diode string for use in the power-rail ESD clamp... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3160928