Low leakage data retention flip flop

Details Low leakage data retention flip flop Low leakage data retention flip flop

2008-04-10

2011-12-13

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000

Reexamination Certificate

active

08076965

ABSTRACT:
A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.

REFERENCES:
patent: 5982211 (1999-11-01), Ko
patent: 7123068 (2006-10-01), Hoover et al.
patent: 7183825 (2007-02-01), Padhye et al.
patent: 2006/0152267 (2006-07-01), Ramprasad

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