Low leakage clamp for E.S.D. protection

Details Low leakage clamp for E.S.D. protection Low leakage clamp for E.S.D. protection

1999-11-29

2002-08-27

Huynh, Kim (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000, C361S054000

Reexamination Certificate

active

06442008

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to the fabrication of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs or MOS) integrated circuits (ICs), and more particularly to the fabrication of Complementary MOS (CMOS) ICs having vertical PNP bipolar transistors providing electrostatic discharge (ESD) protection for input/output (IO) power and ground pads.
As is known in the art, complex high speed IC circuits may require voltage clamps on IO pads to provide protection from sudden voltage swings outside of the designed values for sensitive MOS transistors. Such voltage swings may be caused by power supply instability, or by electrostatic discharge (ESD). ESD may be due to ungrounded human contact with the IC, for example, after walking on carpeting. ESD may cause MOS devices to suffer gate oxide rupture, causing current leakage and defective IC operation.
Current trends in MOS device design tend to increase the device sensitivity to ESD and other voltage swings. A MOS transistor may operate faster if the gate oxide thickness is reduced. However, thinner gate oxide also means greater sensitivity to typical voltage spikes which may destroy the thinner gate oxide. Lower voltage operation of MOS devices may also provide lower power dissipation. Another known method of reducing power dissipation is to use CMOS logic. As is well known in the art, lower power dissipation means lower operating temperatures and better device reliability. Low power dissipation is especially important for portable devices such as cellular phones, personal digital assistants and laptop computers, etc.
There are methods known in the art to provide
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power and ground clamps for low voltage CMOS devices. However, there is a known problem with low powered low voltage CMOS devices because typical voltage clamp protection methods either dissipate too much standby current to be acceptable for low powered CMOS devices, or do not switch enough current away from the CMOS gates to provide the desired level of ESD spike protection. This clamp problem results in an undesirable compromise in CMOS devices between balancing the sharpness of the high voltage cutoff versus the unacceptable amount of standby current generated.
Thus a problem exists in the art of providing rapid ESD protection for IO power and ground supply pads, while minimizing voltage clamp standby power dissipation.
SUMMARY OF THE INVENTION
In accordance with the invention, an integrated circuit input/output power supply voltage clamp is provided, comprising a series of bipolar transistors each having an emitter region electrically connected to either a power pad or to the base region of the preceding transistor. Each one of the bipolar transistors has a collector region electrically connected to a ground supply pad. At least one of the bipolar transistors has the base region connected to one terminal of a capacitor, the second capacitor terminal being connected to ground. The base region is also connected to a resistor network attached to the power supply. With such an arrangement, the chain of bipolar transistors rapidly turn on when the input pad voltage exceeds the safe design limit. Further, the chain of bipolar transistors can conduct a large amount of charge from the power pad to the ground pad, thereby protecting the sensitive MOS circuitry. During standby conditions when the input pad voltage is within safe limits, the capacitor causes the bipolar chain to shut off, thereby reducing the standby power dissipation to acceptable limits for CMOS IC devices. These benefits are provided without complex transistor etworks which increase device size and cost.
In an embodiment of the invention, the string of bipolar transistors is connected in what is known as a Darlington configuration with the first bipolar transistor having the emitter connected to the power supply, and the base connected to the emitter of the next transistor. All of the transistor collectors are part of a common collector connected to ground. The base region of the last transistor is connected to a capacitor network and to a resistor network, connected respectively to ground and power supplies.
In another embodiment of the invention, there is a MOS transistor added to the circuit having a source region connected to both the base of the next to last bipolar transistor as well as to the emitter of the last bipolar transistor. The MOS transistor has a drain region connected to the base of the last bipolar transistor and to the capacitor and resistor networks. This additional MOS transistor provides overshoot and oscillation damping for the initial portion of a rapid voltage spike or static discharge. This transistor provides a current path for the capacitor's over charge to the emitter region of the bipolar transistor.


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