Low latency synchronizer circuit

Details Low latency synchronizer circuit Low latency synchronizer circuit

2009-07-02

2010-11-30

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000

Reexamination Certificate

active

07843244

ABSTRACT:
A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.

REFERENCES:
patent: 5418407 (1995-05-01), Frenkil
patent: 5864252 (1999-01-01), Tran et al.
patent: 6242957 (2001-06-01), Uemura
patent: 6642763 (2003-11-01), Dike
patent: 6724846 (2004-04-01), Lo

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