Low latency switch architecture for high-performance...

Details Low latency switch architecture for high-performance... Low latency switch architecture for high-performance...

2005-01-12

2008-10-07

Shah, Chirag G (Department: 2619)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

07433363

ABSTRACT:
A low latency switch architecture for high performance packet-switched networks which is a combination of input buffers capable of avoiding head-of-line blocking and an internal switch interconnect capable of allowing different input ports to access a single output simultaneously.

REFERENCES:
patent: 5805589 (1998-09-01), Hochschild et al.
patent: 2003/0035371 (2003-02-01), Reed et al.
patent: 2005/0283756 (2005-12-01), O'Dwyer

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