Low-latency method and apparatus of GHASH operation for...

Details Low-latency method and apparatus of GHASH operation for... Low-latency method and apparatus of GHASH operation for...

2011-06-28

2011-06-28

Najjar, Saleh (Department: 2492)

Cryptography

Particular algorithmic function encoding

C726S011000

Reexamination Certificate

active

07970130

ABSTRACT:
Disclosed is a low-latency method and apparatus of GHASH operation for authenticated encryption Galois Counter Mode (GCM), which simultaneously computes three interim values respectively yielded from the additional authenticated data A, the ciphertext C, and the hash key H defined in the GCM. Then, the output of the GHASH operation may be derived. Assuming that A has m blocks and C has n blocks, this disclosure performs the GHASH operation with max {m,n}+1 steps. The input order for the additional authenticated data A and the ciphertext C may be independent. A disordered sequence for the additional authenticated data A and the ciphertext C may also be accepted by this disclosure. This allows the applications in GCM to be more flexible.

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A. Halbuto{hacek over (g)}ullari; Mastrovito Multiplier for General Irreducible Polynomials; Springer-Verlag, Berlin, 1999; pp. 498-507.
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Federal Information Processing Standards Publication 197, Nov. 26, 2001, Announcing the Advanced Encryption Standard(AES).
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High-Speed Hardware Architectures for Authenticated Encryption Mode GCM, Akashi Satoh, ISCAS 2006, pp. 4831-4834.

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