Patent
1994-07-28
1998-05-19
Moore, David K.
395412, G06F 1200
Patent
active
057548196
ABSTRACT:
A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.
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Semiconductor Memories, A Handbook of Design, Manufacture and Application, Betty Prince, Second Ed., John Wiley & Sons.
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"Wired-in Hash Function for Data Cache Address Calculation", IBM TDB, vol. 34. No. 12, May 1992.
Lauterbach Gary R.
Lynch William L.
Caserza Steven F.
Moore David K.
Nguyen Than
Sun Microsystems Inc.
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