Low latency, low power deserializer

Details Low latency, low power deserializer Low latency, low power deserializer

1999-04-29

2003-03-18

Ton, Dang (Department: 2661)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S366000, C370S545000, C370S914000, C375S376000, C341S101000

Reexamination Certificate

active

06535527

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to deserializer circuits generally and, more particularly, to a deserializer circuit that may convert a serial data stream to a parallel data stream and/or a serial clock to a byte clock.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a circuit
10
is shown illustrating a conventional deserializer circuit. The circuit
10
generally comprises a full rate phase-locked loop (PLL)
12
, a framer circuit
14
and a deserializer block
16
. The deserializer block
16
comprises a high speed shifter
18
, a parallel load
20
and a state machine
22
. The circuit
10
has high power consumption due to (i) the high speed shifter
18
, (ii) the parallel load
20
and (iii) the bit rate operation of the state machine
22
and the framer
14
.
Referring to
FIG. 2
, a circuit
10
′ illustrates another conventional deserializer circuit. The circuit
10
′ further comprises a barrel shifter
24
and a register
26
. The circuit
10
′ has a higher operating speed than the circuit
10
due to the implementation of the complex framing function at the parallel word rate (as opposed to bit rate), but has higher latency and still has high power consumption due to (i) the high speed shifter
18
′, (ii) the parallel load
20
′ and (iii) the bit rate operation of the state machine
22
′.
FIG. 3
illustrates the high speed shifter
18
(or
18
′) comprising a number of flip-flops
30
a
-
30
n
. Each of the flip-flops
30
a
-
30
n
is timed by the signal PD_CLK.
The circuit
10
and the circuit
10
′ both require a high speed shifter
18
(and
18
′) and high speed parallel load
20
(and
20
′), which are difficult to implement at high speeds (e.g., at 1 GHz or higher).
SUMMARY OF THE INVENTION
The present invention concerns a first circuit, a deserializer circuit and a framer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may comprise (a) a parallel register bank configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals and (b) a state machine configured to generate the one or more select signals in response to one or more control signals. The framer circuit may be configured to generate the one or more control signals in response to (i) one or more input control signals and (ii) the output signal.
The objects, features and advantages of the present invention include providing a deserializer circuit that may have (i) a low power consumption that may be due to a non-shifting parallelizing element and/or data buffering and/or (ii) a low latency that may be due to a shift mechanism.


REFERENCES:
patent: 5101203 (1992-03-01), Gersbach et al.
patent: 5757297 (1998-05-01), Ferraiolo et al.
patent: 5777567 (1998-07-01), Murata et al.
patent: 5953386 (1999-09-01), Anderson
patent: 5960007 (1999-09-01), Grivna
patent: 5982786 (1999-11-01), Grivna
patent: 6026134 (2000-02-01), Duffy et al.
patent: 6265996 (2001-07-01), Duffy
Cypress HOTLink™ Transmitter/Receiver, CY7B923/CY7B933, Apr. 5, 1999, pp. 1-35.
Duffy, Michael, “Low Latency, Low Power Deserializer”, U.S. Ser. No. 09/301,900, filed Apr. 29, 1999.

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