Low latency inter-reference ordering in a multiple processor...

Details Low latency inter-reference ordering in a multiple processor... Low latency inter-reference ordering in a multiple processor...

2005-06-07

2005-06-07

Lane, Jack (Department: 2188)

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

C709S213000, C710S316000, C710S317000, C370S357000, C370S360000, C370S368000

Reexamination Certificate

active

06904465

ABSTRACT:
A multiple-processor system in which a commit message is returned to a source processor that requests a memory access operation so as to indicate the apparent completion of the operation includes a multiple-level switch unit linking nodes that contain the processors. The switch unit includes multiple input switches each of which receives messages from multiple nodes, and a set of output switches whose inputs are the outputs of the input switches and whose outputs are the inputs of the nodes. Each switch processes messages in the order in which they are received by the switch and each output switch follows the same rule as the other output switches.

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