Low latency, high clock frequency plesioasynchronous packet-base

Details Low latency, high clock frequency plesioasynchronous packet-base Low latency, high clock frequency plesioasynchronous packet-base

1996-02-22

1998-11-17

Kizou, Hassan

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370422, H04L 1256

Patent

active

058386840

ABSTRACT:
An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.

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"Hybrid Switch for a Highly Parallel Message Passing System", IBM Technical Disclosure Bulletin, vol. 33, No. 1A, pp. 214-217, Jun. 1, 1990.

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