Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
2007-05-09
2010-11-02
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C703S002000, C703S022000, C712S001000, C709S239000, C370S390000, C370S402000
Reexamination Certificate
active
07827024
ABSTRACT:
Methods, parallel computers, and computer program products are disclosed for low latency, high bandwidth data communications between compute nodes in a parallel computer. Embodiments include receiving, by an origin direct memory access (‘DMA’) engine of an origin compute node, data for transfer to a target compute node; sending, by the origin DMA engine of the origin compute node to a target DMA engine on the target compute node, a request to send (‘RTS’) message; transferring, by the origin DMA engine, a predetermined portion of the data to the target compute node using memory FIFO operation; determining, by the origin DMA engine whether an acknowledgement of the RTS message has been received from the target DMA engine; if the an acknowledgement of the RTS message has not been received, transferring, by the origin DMA engine, another predetermined portion of the data to the target compute node using a memory FIFO operation; and if the acknowledgement of the RTS message has been received by the origin DMA engine, transferring, by the origin DMA engine, any remaining portion of the data to the target compute node using a direct put operation.
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Archer Charles J.
Blocksome Michael A.
Ratterman Joseph D.
Smith Brian E.
Biggers & Ohanian LLP
International Business Machines - Corporation
Phan Thai
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