Low latency fused multiply-adder

Details Low latency fused multiply-adder Low latency fused multiply-adder

1998-12-08

2001-08-28

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S501000

Reexamination Certificate

active

06282557

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to an apparatus for performing both multiplication and addition. Still more particularly, the present invention relates to a low latency fused multiply-adder.
2. Description of the Prior Art
Fused multiply-adders combine a multiplication operation with an add operation. Within a fused multiply-adder, a multiplicand and a multiplier are initially multiplied via a partial product generation module. The partial products are then added by a partial product reduction module that reduces the partial products to a Sum and a Carry in their redundant form. The redundant Sum and Carry are further added to an addend via a carry-save adder to form another redundant Sum and Carry. The second redundant Sum and the second redundant Carry are subsequently added within a carry-propagate adder to yield a Sum Total.
While a prior art multiply-add operation performed by a fused multiply-adder typically has a lower latency than the combined latencies of individual multiplication operation and addition operations, the present invention recognizes that the configuration of a prior art fused multiply-adder contributes to an increase in the latency of multiplication operations. Consequently, it would be desirable to provide an improved fused multiply-adder with a low latency multiplication operation.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.
All features and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 3761698 (1973-09-01), Stephenson
patent: 4594678 (1986-06-01), Uhlenhoff
patent: 4852037 (1989-07-01), Aoki
patent: 4969118 (1990-11-01), Montoye et al.
patent: 5751619 (1998-05-01), Agarwal et al.

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