Low latency dynamic random access memory

Details Low latency dynamic random access memory Low latency dynamic random access memory

2000-02-23

2001-05-01

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S149000, C365S230050

Reexamination Certificate

active

06226223

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a dynamic random access memory (DRAM), for example.
Hereinafter, a “low latency DRAM cell” using dual word lines and dual bit lines as disclosed in U.S. Pat. No. 5,856,940 will be described with reference to FIG.
20
. Each cell of the low latency DRAM includes two transistors as transfer devices and a single storage capacitor as a charge storage device. And each memory cell is connected to two word lines and two bit lines.
FIG. 20
illustrates a circuit configuration for a low latency DRAM cell
100
in the known semiconductor memory device. AS shown in
FIG. 20
, the memory cell
100
includes first and second transistors
102
and
103
and a storage capacitor
104
. The gate, drain and source of the first transistor
102
are connected to a first word line WLa, a first bit line BLa and a storage node
101
, respectively. The gate, drain and source of the second transistor
103
are connected to a second word line WLb, a second bit line BLb and the storage node
101
, respectively. One of the two electrodes of the storage capacitor
104
is connected to the storage node
101
, while the other electrode thereof serves as a cell plate.
As can be seen, the memory cell
100
includes two independently controllable transistors
102
and
103
for one storage node
101
. Accordingly, interleaving is possible between accessing the memory cell
100
using the first word line WLa, first transistor
102
and first bit line BLa and accessing the memory cell
100
using the second word line WLb, second transistor
103
and second bit line BLb. That is to say, while one of the two bit lines is being precharged, the memory cell
100
can be accessed using the other bit line. Thus, reading and writing can be performed at high speeds.
In a memory cell with such a configuration, one of the first and second transistors
102
and
103
should be activated by selecting one of the word lines WLa and WLb to start reading or writing. In selecting the word line, a select signal should be externally input from the outside of the semiconductor memory device or two clock signals should be input externally.
To input the select signal externally, however, a circuit for generating the select signal should be provided outside. Also, if the two clock signals need to be input externally from the outside of the semiconductor memory device, then a circuit for generating these two clock signals must be provided outside. Furthermore, any of these requirements leads to an increase in number of input terminals.
SUMMARY OF THE INVENTION
An object of the present invention is providing a semiconductor memory device with multiple low latency DRAM cells, each of which includes a charge storage device and first and second transfer devices connected to the storage device for transferring charge through different data input/output lines, and which are accessible without supplying any particular select signal or two clock signals externally.
A semiconductor memory device according to the present invention includes multiple memory cells. Each of these memory cells includes a charge storage device and first and second transfer devices. The first transfer device is driven by a first word line and connected between the charge storage device and a first data input/output line for transferring charge. The second transfer device is driven by a second word line and connected between the charge storage device and a second data input/output line for transferring charge. The memory device further includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of the first word lines and one of the second word lines are activated alternately.
According to the present invention, the first transfer device, which is driven by one of the first word lines, and the second transfer device, which is driven by one of the second word lines, can be activated alternately responsive to the first and second clock signals generated by the clock generator. Thus, there is no need to provide the select signal or two clock signals externally in performing such an operation.
In one embodiment of the present invention, the clock generator adaptively changes levels of the first and second clock signals based on a level change of a reference clock signal input externally.
In such an embodiment, the first and second clock signals can be generated in synchronism with the reference clock signal.
In another embodiment of the present invention, the clock generator includes means for suspending the level changes of the first and second clock signals.
In such an embodiment, the memory cells and their peripheral circuitry can be deactivated by suspending the level changes of the first and second clock signals, thus reducing the power dissipation of the semiconductor memory device.
In still another embodiment, the clock generator includes means for making the first and second clock signals change into respectively predetermined levels when these signals change their levels for the first time.
In such an embodiment, when the memory device starts to operate, a particular one of the transfer devices in each memory cell can be activated earlier. Thus, it is possible to control which transfer device should be selected at a particular point in time without inputting any additional select signal.
In still another embodiment, the clock generator includes means for suspending the level changes of the first and second clock signals unless the memory device is accessed.
In such an embodiment, only when a memory cell is accessed, the clock generator changes the levels of the first and second clock signals and activates the memory cell and its peripheral circuit, thus reducing the power dissipation of the semiconductor memory device.
In still another embodiment, the memory device further includes an address comparator for detecting a change of row addresses. If the address comparator has sensed that a previous row address has been replaced with a new row address, then there is an interval during which one of the word lines that is associated with the previous row address and another one of the word lines that is associated with the new row address are both activated. On the other hand, if the address comparator has sensed no row address change, then there is no interval during which the first and second word lines that are associated with a current row address are both activated.
In such an embodiment, the first transfer devices of memory cells belonging to a certain row and the second transfer devices of memory cells belonging to another row can be activated simultaneously, while the first and second transfer devices in the same memory cell are not activated at the same time.
In still another embodiment, if the address comparator has sensed no row address change, then an activated one of the first and second word lines that are associated with a current row address is deactivated at a first time. Alternatively, if the address comparator has sensed that a previous row address has been replaced with a new row address, then an activated one of the word lines that is associated with the previous row address is deactivated at a second time. In this case, an interval between a reference point in time the address comparator made a comparison and the first time is shorter than an interval between the reference point and the second time.
In such an embodiment, an activated one of the first and second transfer devices in the same memory cell can be deactivated first, and then the other transfer device can be activated.
In still another embodiment, if the address comparator has sensed no row address change, then the changes in signal levels on the first and second word lines are suspended.
In such an embodiment, while one of the first and second word lines associated with the same row address is activated, the other word line is not activated.


REFERENCES:
patent: 5010519 (1991-04-01), Yoshimoto et

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