Low-latency DC compensation

Details Low-latency DC compensation Low-latency DC compensation

2007-12-25

2007-12-25

Nguyen, Simon (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

C455S063100, C455S067130, C455S234100, C455S296000, C375S319000

Reexamination Certificate

active

10909166

ABSTRACT:
A method of performing DC estimation and correction in the presence of an automatic gain control function introduces no long-term delay of the signal. When the automatic gain control function indicates that it has altered the gain or when an initial DC estimate is required after switch-on, a new DC estimate is begun. Input samples received at the signal-sampling rate are stored in a first-in first-out buffer, while waiting for sufficient samples to have been received to perform the DC estimate. Once sufficient samples have been received to calculate a DC estimate, the data that has been stored in the FIFO is read out and processed by subsequent signal processing functions at a higher rate than the data-sampling rate. Due to the higher rate of read-out, the FIFO is rapidly emptied so that the subsequent signal processing functions “catch up” with the input data stream leading to no long-term latency.

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