Low latency architecture for spatial filtration

Details Low latency architecture for spatial filtration Low latency architecture for spatial filtration

1998-04-01

2000-04-04

Rogers, Scott

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382304, G06T 500, G06K 940

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060470917

ABSTRACT:
A spatial filter having coefficients selected and distributed within an array, so that when the array is divided non-diagonally into four equal quadrants, (1) the coefficients are of constant sign within each quadrant; (2) coefficients in diagonally opposed quadrants have like sign; and (3) coefficients in non-diagonally neighboring quadrants have unlike sign. In a preferred embodiment, coefficients cause the array to form a "saddle" shape when the coefficient values are representative of the local slope on a surface described by the array. This "saddle" shape enables improved filtration properties. The inventive spatial filter is further advantageously embodied in architecture comprising an array of individual calculation modules corresponding to the filter array. Rows of modules are coupled together in parallel. The input signal is fed to each row concurrently via FIFO buffers, enabling concurrent calculation operations. After calculation, output values for each module are accumulated and summed, the result being placed into an output stream. The FIFO buffers then present the next input values in the input stream to the calculation modules, and so on. The result is a low-latency "streaming" filtration that is further economical on hardware, requiring only FIFO storage resources. Advantageously, the entire inventive filter may be conveniently deployed as a digital signal processor ("DSP") on a unitary integrated circuit chip.

REFERENCES:
patent: 3964021 (1976-06-01), Tamches
patent: 4799055 (1989-01-01), Nestler et al.
patent: 4885787 (1989-12-01), Okamoto et al.
patent: 5027423 (1991-06-01), Kawata et al.
patent: 5912744 (1999-06-01), Nakane

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