Low junction capacitance semiconductor structure and I/O buffer

Details Low junction capacitance semiconductor structure and I/O buffer Low junction capacitance semiconductor structure and I/O buffer

1999-10-06

2002-07-16

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

C257S406000, C257S386000, C257S336000, C257S376000, C257S335000, C257S344000, C257S548000, C257S408000, C257S156000, C257S549000, C257S360000

Reexamination Certificate

active

06420774

ABSTRACT:

BACKGROUND OF THE INVENTION
DESCRIPTION OF THE INVENTION
The present invention relates to a semiconductor device, and in particular, to a low junction capacitance semiconductor structure and an I/O buffer, in which the junction capacitance of the semiconductor structure and the input capacitance of the I/O buffer can be both reduced.
In advanced technologies, speed performance and driving capacity are both important specifications for chip designs. However, a large driving capacity usually means a large device width which consumes a large junction capacitance. Especially for ESD circuits, most designers keep a large spacing between contacts and poly gates, thus increasing the junction capacitance with the increasing of the device width. Further, the increasing junction capacitance will also impact the hi-speed performance and reduce the design window.
FIG. 1
(Prior Art) is a sectional diagram showing a conventional complementary I/O buffer I
1
which is formed on a semiconductor substrate, such as a P-type silicon substrate
10
. In
FIG. 1
, the complementary I/O buffer I
1
includes an NMOS transistor N
1
and a PMOS transistor P
1
. The NMOS transistor N
1
is formed in the P-type silicon substrate
10
. The PMOS transistor P
1
is formed in an N-well
20
which is formed on the P-type silicon substrate
10
. The NMOS transistor N
1
has a gate
12
and N-type source and drain regions
14
,
16
formed aside the gate
12
. The PMOS transistor P
1
has a gate
22
and P-type source and drain regions
24
,
26
formed aside the gate
22
. The drain region
16
of the NMOS transistor N
1
and the drain region
26
of the PMOS transistor P
1
are connected through contact windows
31
to a pad
30
. The pad
30
is then connected as an I/O terminal of the complementary I/O buffer I
1
.
FIG. 2
(Prior Art) is an equivalent circuit diagram of the complementary I/O buffer I
1
in FIG.
1
. As shown in
FIG. 2
, when a low voltage is input to the gate
22
of the PMOS transistor P
1
, a positive voltage from the positive voltage source VD will be transferred to internal circuits though the PMOS transistor P
1
, the pad
30
and a resistor R connecting to the internal circuits. On the contrary, when a high voltage is input to the gate
12
of the NMOS transistor N
1
, a negative voltage from the negative voltage source V
ss
will be transferred to the internal circuits though the NMOS transistor N
1
, the pad
30
and the resistor R.
For this case, to prevent leakage currents due to the shortening of the poly gates in advanced technologies, the concentration for anti-punch through implant is usually increased, thus increasing the junction capacitance. In other circuits, such as ESD circuits, to improve driving capacity and ESD endurance, size and layout area for MOS transistors are also increased, thus increasing the junction capacitance of the MOS transistors (Cjp for the PMOS transistor P
1
and Cjn for the NMOS transistor N
1
). Therefore, the parasitic junction capacitance connecting to the pad
30
may reach as high as 5 pF, which will severely impact the hi-speed performance of input signals. As a consequence, it is necessary to limit the parasitic junction capacitance connecting to the pad in advanced IC designs. For example, in RAMBUS DRAM specifications, the parasitic junction capacitance connecting to the pad is limited to less than 2.4 pF so that the hi-speed requirements can be satisfied.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a low junction capacitance semiconductor structure and an I/O buffer, in which the junction capacitance of the semiconductor structure and the input capacitance of the I/O buffer are both reduced, thus improving its hi-speed performance.
It is another object of the present invention to provide a low junction capacitance semiconductor structure and an I/O buffer, in which the occupied chip area is greatly reduced without losing any driving capacity and ESD endurance.
To achieve above and other objects, the present invention provides a low junction capacitance semiconductor structure. This semiconductor structure includes a MOS transistor and a lightly doped region. The MOS transistor is formed on a semiconductor substrate, and has a gate and source and drain regions formed aside the gate. The lightly doped region has a conductivity the same as the source/drain regions, and is formed immediately below the drain region of the MOS transistor.
In this semiconductor structure, the semiconductor substrate can be a P-type silicon substrate, and the source and drain regions and the lightly doped region can be N-type.
Or, in this semiconductor structure, the semiconductor substrate can be an N-type silicon substrate, and the source and drain regions and the lightly doped region can be P-type.
Further, the present invention also provides a low junction capacitance semiconductor structure. This semiconductor structure includes a MOS transistor, a lightly doped region and a deeply doped region. The MOS transistor is formed in a well, and has a gate and source and drain regions formed aside the gate. The lightly doped region has a conductivity the same as the source and drain regions, and is formed immediately below the drain region of the MOS transistor and has a depth equal to the well. The deeply doped region having a conductivity the same as the well is then formed at the bottom of the lightly doped region to isolate the lightly doped region and the semiconductor substrate.
In this semiconductor structure, the well and the deeply doped region, are N-type, and the source and drain regions and the lightly doped region are P-type. Or, in this semiconductor structure, the well and the deeply doped region are P-type, and the source and drain regions and the lightly doped region are N-type.
Further, the present invention also provides a low junction capacitance I/O buffer. This I/O buffer includes a semiconductor substrate, a well, a first transistor, a second transistor, a first lightly doped region, a second lightly doped region and an I/O terminal. The well is formed at a predetermined location on the semiconductor substrate. The first transistor is formed on the semiconductor substrate, and has a first gate and first source and drain regions aside the first gate. The second transistor is formed on the well, and has a second gate and second source and drain regions aside the second gate. The first lightly doped region is formed immediately below the first drain regions, and has a conductivity the same as the first source and drain regions of the first transistor. The second lightly doped region is formed immediately below the second drain region, and has a conductivity the same as the second source and drain regions and has a depth equal to the well. The I/O terminal is then connected between the first drain region of the first transistor and the second drain region of the second transistor.
In this I/O buffer, a deeply doped region can be further formed at the bottom of the second lightly doped region in the well to isolate the lightly doped region and the semiconductor substrate.


REFERENCES:
patent: 5008723 (1991-04-01), Van der Have
patent: 5759901 (1998-06-01), Loh et al.
patent: 5777368 (1998-07-01), Wu et al.
patent: 6051860 (2000-04-01), Odanaka et al.
patent: 6150699 (2000-11-01), Wakabayashi

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