Low jitter phase-locked loop with duty-cycle control

Details Low jitter phase-locked loop with duty-cycle control Low jitter phase-locked loop with duty-cycle control

1999-10-12

2002-03-12

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S156000, C327S294000, C375S376000

Reexamination Certificate

active

06356129

ABSTRACT:

This application relates generally to automatic test equipment, and more particularly to timing circuits for testing electronics in automatic test systems.
Recent developments in mixed-signal products for multimedia video, data conversion, and the Internet have spurred a demand for faster, more accurate, and more complex systems for testing these products. “Mixed-signal” products provide a mix of analog and digital functionality and include, for example, analog-to-digital converters, digital-to-analog converters, modems, disk drive controllers, transceiver links, digital radios, and high-speed interpolators. To test mixed-signal products, automatic test equipment (ATE) generally supplies both analog and digital test resources, often simultaneously, and at high speed.
FIG. 1
illustrates a setup for testing an analog-to-digital converter (ADC), a common mixed-signal product. A unit under test (UUT)
112
includes an ADC
114
connected to a test system
110
. The test system supplies an analog signal to the ADC via an analog source
116
, and receives digital codes from the ADC via digital I/O
120
. A clock
118
provides a clock signal to the ADC
114
. If the ADC is operating properly, the digital codes produced by the ADC represent the states of the analog signal at instants in time defined by the clock
118
. For each active edge of the clock
118
, the ADC performs a new conversion of the analog signal, and produces a new digital output value—a process called “sampling.” Typically, the test system
110
also includes a computer (not pictured) that reads the digital values from the digital I/O
120
, and tests them to verify that the ADC is operating properly.
Testing mixed-signal devices such as the ADC of
FIG. 1
customarily involves varying the frequency of the sample clock signal to approach or exceed the device's maximum specified rate. We have recognized that it would also be desirable to vary the duty cycle and pulse width of the sample clock signal. Mixed-signal devices often specify characteristics such as signal-to-noise ratio (SNR) and distortion. These characteristics vary as a function of the duty cycle or pulse width of the applied sample clock. The ability to vary the duty cycle and pulse width of the sample clock would thus facilitate mixed-signal testing and characterization.
Like all electronic devices, mixed-signal devices inherently generate noise. As shown in
FIG. 2
b,
an ADC receiving an input signal that consists of three pure tones produces a power spectrum revealing these three tones, plus a plurality of noise components. Compared with this actual power spectrum, the power spectrum of an ideal, theoretical ADC shown in
FIG. 2
a
generates no noise.
One of the ways in which noise manifests itself in ATE systems is in the form of “jitter” on the clock signal. “Jitter” is a timing error of a periodic signal, measurable in seconds, and observable as random movements in time of signal edges from cycle to cycle, relative to their ideal, or average, positions.
FIGS. 3-5
illustrate the effects of jitter on digital values read back from an ideal ADC, configured in the manner shown in FIG.
1
.
FIG. 3
illustrates an ideal case: a pure tone
318
is sampled by the ideal ADC with a jitterless clock signal
312
to produce a discrete time representation
310
. As there is no jitter, the sampling period
316
is perfectly regular between any two adjacent clock pulses. In
FIG. 4
, the same ideal ADC samples the same pure tone
318
; however, the sampling clock suffers from jitter. The jitter appears as irregularity in the intervals between adjacent pulses
416
of the clock signal
412
. Although the sampled values
414
perfectly represent the values of the input tone
318
at the instant that each sample is taken, the spacing of the sampled values
414
is irregular.
FIG. 5
illustrates the effect of the jitter of
FIG. 4
on a typical test system. The sampled data
510
is the same as the data
410
of
FIG. 4
, except that the data has been regularly spaced. Absent a way of correcting for clock jitter, an ATE system will process the sampled data as if the edges occurred regularly—exactly as shown in FIG.
5
. In contrast with the perfect tone
318
that was sampled, the output values
510
contain noise. As far as the ATE can determine, the effects of clock jitter are indistinguishable from amplitude noise in the ADC or analog source.
Previous techniques have attempted to reduce jitter in mixed-signal testing. According to one technique, a free-running crystal oscillator is used in place of the ATE clock
118
. The free-running crystal is connected directly to the UUT's clock input, in a manner similar to FIG.
1
. Crystal oscillators are inherently stable and are commercially available with very low jitter. Therefore, the free-running, crystal oscillator technique typically reduces ATE-induced jitter.
Because the crystal oscillator is “free-running,” however, its period is not inherently synchronized with the period of the ATE clock, i.e., the two clocks are not “coherent.” The ADC makes a new conversion upon each active edge of the crystal oscillator, but the digital I/O
120
retrieves values from the ADC under the control of a separate, ATE clock. Non-coherency adds noise to sampled data.
FIG. 6
a
shows the power spectrum of a pure tone sampled by an ideal ADC and clocked by an ideal crystal oscillator, but read by a non-coherent ATE clock. The resulting power spectrum reveals distinctive “skirts” around the input tone.
FIG. 6
b
shows a power spectrum acquired under identical conditions, except the two clocks are coherent. Compared with the power spectrum produced by the coherent clocks, the power spectrum produced by the non-coherent clocks is broader. The broader spectrum requires more time to process and thus reduces tester throughput.
With the free-running clock technique, errors are also introduced by “windowing” of the input signal. “Windowing” is a well-known DSP algorithm in which data is collected over a predetermined time interval and multiplied sample-by-sample by a window function. The free-running clock technique requires windowing because the analog source
116
is not inherently synchronized with the clocking of the ADC. Thus, the ATE has no direct control over when a complete period of the input signal has been sampled. Windowing cuts off periodic signals in mid-stream, and distorts the power spectra of sampled signals.
A second approach to reducing clock jitter is disclosed by Fang Xu in international patent application number PCT/US97/10753, filed Jun. 26, 1997, published Dec. 30, 1998, and assigned to Teradyne, Inc. In that application, Xu discloses a high-Q band-pass filter built from an array of quarter-wavelength, transmission line stubs. The filter is connected in series between a digital channel of the ATE (or other signal source) and the UUT. Xu's filter works by passing a predetermined fundamental frequency and its odd harmonics, but attenuating all other frequencies. Perfect square waves contain odd harmonics only. Thus, Xu's filter passes square waves unattenuated. Duty cycles that are different from 50% correspond to even harmonics, however, and Xu's filter eliminates them. As jitter equates to random changes in the duty cycle, Xu's filter reduces jitter while preserving square wave shape and edge speed.
Because its frequency response is fixed by the geometry of its constituent parts, Xu's filter generally operates at one frequency only. This limitation negatively impacts ATE programs, which preferably test devices over a range of operating conditions. Although it is possible to modify Xu's filter to produce variable frequencies, the modified filters tend to be large. Xu's filters also become larger for lower frequency signals. As space tends to be short near the UUT in ATE systems, Xu's filter is not practical where low, or variable, frequencies are desired. In addition, Xu's filter specifically blocks duty cycles that are different from 50%, and is thus impra

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