Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2002-01-10
2004-02-10
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S016000, C331S03600C, C327S156000, C327S157000
Reexamination Certificate
active
06690240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to phase-locked loop (“PLL”) circuits, and, more particularly, to a loop filter for a PLL circuit. More specifically, the present invention relates to a low-jitter loop filter for a PLL circuit.
2. Description of Related Art
A phase-locked loop (“PLL”) circuit generally includes a phase detector, a loop filter, and a controlled oscillator. The phase detector receives an input signal, which has a reference frequency. The output signal of the controlled oscillator is fed back to the phase detector. The frequency of the output signal is typically a multiple of the reference frequency of the input signal. The PLL circuit is utilized to lock the output frequency to the input frequency. Locking the output frequency to the input reference frequency is critical in various applications, such as developing accurate and precise clocks for digital signal processors (“DSPs”) and for audio sampling frequencies and rates. Fast locking applications also exist in which adaptive bandwidth PLLs have been developed and used.
PLL circuits in mixed-signal integrated circuit designs typically operate in noisy environments. Much of the noise is introduced through the current or voltage supplies, the substrate, temperature variations, process parameters, or other such sources. Low jitter PLL circuits require high loop bandwidths to reject the noise.
Passive loop filters for PLL circuit designs are popular due to their simplicity, but the control of their loop time constants lacks flexibility. Active loop filters used in conjunction with feed-forward charge pumps provide a wider range of loop time constants and often provide a decreased area of on-chip capacitance. Fully differential charge pumps for PLL circuit designs have been of great interest due to their ability to reject noise. However, fully differential charge pumps require increased on-chip capacitance and extra circuitry for common mode feedback. One drawback of a charge pump PLL circuit is that setting the loop filter pole position requires a compromise between the loop phase margin and the jitter performance.
Typical charge pump PLL circuits having two poles at the origin require a zero to be introduced in the loop for stability. A common method of adding a zero is to couple a resistor in series with the charge pump capacitor or by using a feed-forward technique. Most charge pump PLLs use a proportional signal that is based on the instantaneous phase difference. The signal in lock is characterized by narrow high amplitude pulses, that even after filtering, lead to an abrupt variation of the oscillator control signal and rapid frequency changes that degrade the jitter performance of the PLL circuit.
With reference now to
FIG. 1
, an exemplary phase-locked loop (“PLL”) circuit
100
according to the prior art is shown. PLL circuit
100
includes a phase frequency detector (“PFD”)
104
, a charge pump (“CP”)
106
, a loop filter
108
, and a controlled oscillator (“CO”)
116
coupled together in series. An N divider
102
is coupled to an input of the PFD
104
. An M divider
118
is coupled to the output of the CO
116
, and the output of M divider
118
is coupled and fed back to another input of the PFD
104
. An input signal
101
is fed into N divider
102
and divides input signal
101
by a factor of N to provide input reference signal
103
. The N-divided input reference signal
103
is fed as an input signal into PFD
104
. Furthermore, an output signal
120
of PLL circuit
100
is fed into an M divider
118
as shown in
FIG. 1. M
divider
118
divides output signal
120
by a factor of M to provide an input feedback signal
105
.
PFD
104
compares the frequencies or phases of input reference signal
103
and feedback signal
105
. PFD
104
generates and outputs a phase error signal to CP
106
. The phase error signal is the difference in phase between what the phase of the signal currently is (e.g., phase of feedback signal
105
) and what the phase of the signal should be (e.g., phase of the input reference signal
103
). The phase error signal may be passed onto loop filter
108
in terms of a current value (e.g., charge stream) from CP
106
. Loop filter
108
filters currents from CP
106
by passing some current signals at certain frequencies while attenuating other current signals at other frequencies. Loop filter
108
provides and outputs a control signal to tune the phase of the output signal
120
based on any difference between the control signal and a normal operating or optimum signal. The control signal is input into CO
116
to provide an output phase for output signal
120
that the loop will lock with the reference phase of input reference frequency
101
.
Loop filter
108
, which is an exemplary loop filter according to the prior art, has a proportional signal path
107
and an integral signal path
109
. Proportional signal path
107
includes a resistor
110
having one node coupled to the output of CP
106
and the other node coupled in series to a node of a proportional path capacitor
112
. The other node of proportional path capacitor
112
is coupled to ground. Integral signal path
109
includes an integral path capacitor
114
. One node of integral path capacitor
114
is also coupled to the output of CP
106
, and the other node of integral path capacitor
114
is coupled to ground. Proportional signal path
107
generates a proportional signal that is based on the instantaneous phase difference. Integral signal path
109
provides an integral signal, which tracks the overall input signal level that includes past proportional input signals. Loop filter
108
generates and outputs the control signal, which is the sum of the present proportional signal with the overall signal level, to CO
116
. CO
116
, in turn, generates output signal
120
having an output phase that the loop will lock with the reference phase of input reference frequency
103
.
Referring now to
FIG. 2
, an exemplary graph
200
showing ideal signals or pulses
206
,
208
, and
210
generated by proportional path
107
of loop filter
108
according to the prior art is depicted. In exemplary graph
200
, proportional path signal
202
is plotted against time
204
. When PFD
104
of PLL circuit
100
detects instantaneous phase differences, proportional path
107
of loop filter
108
outputs pulses
206
,
208
, and
210
to CO
116
. Pulses
206
,
208
, and
210
vary in width based on the magnitudes of the detected phase differences (e.g., from larger to smaller pulses based on respective larger to smaller magnitudes of phase differences). As shown in
FIG. 2
, pulses
206
,
208
, and
210
occur in the early portions of update periods (“Tupdates”)
205
. The signal levels then return to a zero level for the remaining portions of Tupdates
205
.
As stated earlier, pulses
206
,
208
, and
210
based on instantaneous phase differences lead to abrupt variations of the signal of CO
116
and rapid frequency changes that degrade the jitter performance of PLL circuit
100
. With reference now to
FIG. 3
, an exemplary graph
300
illustrating the input signal to CO
116
from loop filter
108
according to the prior art is depicted. In exemplary graph
300
, CO input signal
302
is plotted against time
304
. Exemplary graph
300
shows integral path signal
308
plotted against time
304
. Integral path signal
308
only sums the past pulses but is not substantially affected by any single pulse
206
,
208
, or
210
of proportional path
107
. Exemplary graph
300
further shows proportional path signal
310
and the total CO input signal
306
having waveforms with jitter that is attributed to pulses similar to pulses
206
,
208
, and
210
of proportional path
107
. The jitter occurs both in the unlocked and locked periods of PLL circuit
100
. As shown in
FIG. 3
, the pulses therefore negatively affect the overall jitter performance of PLL circuit
100
.
It is well known in the art that signals for a PLL circuit can be either voltage s
Hagge Melvin L.
Maxim Adrian
Schneider Edmund M.
Scott, III Baker
Cirrus Logic Inc.
Kinkead Arnold
Lin, Esq. Steven
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