Low jitter large frequency tuning LC PLL for multi-speed...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

Reexamination Certificate

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C331S008000, C331S016000, C331S025000

Reexamination Certificate

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08044724

ABSTRACT:
The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

REFERENCES:
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patent: 6441660 (2002-08-01), Ingino, Jr.
patent: 7079616 (2006-07-01), Castiglione et al.
patent: 7135934 (2006-11-01), Sanchez et al.
patent: 7408419 (2008-08-01), Ko
patent: 7554416 (2009-06-01), Lee et al.
patent: 2002/0039050 (2002-04-01), Griffith et al.
patent: 2003/0016088 (2003-01-01), Scheffler
patent: 2006/0284689 (2006-12-01), Gomez
patent: 2008/0007365 (2008-01-01), Venuti et al.

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