Low jitter high phase resolution PLL-based timing recovery...

Details Low jitter high phase resolution PLL-based timing recovery... Low jitter high phase resolution PLL-based timing recovery...

2004-09-10

2009-12-22

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S158000

Reexamination Certificate

active

07636007

ABSTRACT:
A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

REFERENCES:
patent: 5243599 (1993-09-01), Barrett et al.
patent: 5521499 (1996-05-01), Goldenberg et al.
patent: 5570059 (1996-10-01), Vora et al.
patent: 5805003 (1998-09-01), Hsu

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