Low jitter fractional divider with low circuit speed constraint

Details Low jitter fractional divider with low circuit speed constraint Low jitter fractional divider with low circuit speed constraint

1999-11-16

2001-04-10

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S028000

Reexamination Certificate

active

06215839

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fractional divider and, more particularly, to a low jitter fractional divider with low circuit speed constraint.
2. Description of Related Art Conventionally, a fractional divider is provided to divide the frequency of a clock signal by a fraction number “b/a”, wherein b>a. Such a fractional divider is implemented by employing an accumulator to add the value of “a” to the value stored in the accumulator in each operation cycle. The accumulated value is compared with the value of “b”. In case of a>b, the accumulated value is subtracted by the value of “b” and re-stored to the accumulator, and an overflow flag is generated. Otherwise, the accumulated value is simply re-stored to the accumulator. This overflow flag is provided to be the output of the fractional divider.
FIG. 4
shows that such a fractional divider
41
is used to divide a clock signal “ck” by 5/3 to generate a divided clock signal “ck′”. Based on the operating manner of the fractional divider
41
as described above, a timing diagram is obtained, which illustrates that five continuous pulses of the clock signal “ck” are applied to the fractional divider
41
to generate three continuous pulses of clock signal “ck′”. Therefore, a divide-by-5/3 operation is performed. However, the pulses of the clock signal “ck′” generated by the fractional divider
41
are not uniformly distributed, which is known as a jitter phenomenon in the art. Such jitter is especially obvious if the clock frequency to be divided is low. To overcome this jitter problem, the conventional technique employs a high frequency base clock signal and an accumulator for implementing a fractional divider to obtain a low jitter clock signal. However, when the stages of the accumulators are increased and the frequency of the base clock signal goes higher, the accumulator will not be able to finish the required accumulation operation in a short operation cycle, due to the limitation imposed by the current integrated circuit manufacturing process. Accordingly, a bottleneck is encountered with the increase of a clock signal. In addition, it may be applicable to reduce the frequency of a high-frequency clock signal prior to performing the fractional division operation, thereby avoiding the bottleneck. Unfortunately, this will increase the jitter as described above. Therefore there is a need to have a fractional divider which can mitigate and/or obviate the aforementioned problems.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a low jitter fractional divider with low circuit speed constraint, which is triggered by a clock signal with a relatively low frequency to perform a fractional division process, such that the bottleneck in circuit speed can be eliminated and a low jitter as achieved in a high frequency fractional division process can be maintained.
To achieve the object, the low jitter fractional divider with low circuit speed constraint in accordance with the present invention includes a divider, a fractional divider, and a compensation circuit. The divider is provided to divide the frequency of an input first clock signal by an integer number c to obtain a second clock signal. The fractional divider divides the frequency of the second clock signal by a fraction number b/a to obtain an output voltage signal. The compensation circuit has an adjust buffer and a down-counter for receiving the output voltage signal to generate an output clock signal with low jitter. The adjust buffer generates an adjust signal based on the output voltage signal and the feedback of the output clock signal, wherein the adjust buffer has a value which is decreased when the output voltage signal asserts a pulse, until reaching a predetermined minimum value, and a value which is increased when the output clock signal asserts a pulse until reaching a predetermined maximum value. The down-counter is driven by the first clock signal to perform a counting operation for generating the output clock signal, wherein the down-counter is loaded with a count value determined by c, a, and b, based on the adjust signal and the feedback of the output clock signal when a zero value is reached in the down-counter, thereby adjusting the output clock signal to reduce jitter.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

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