Low jitter digital frequency synthesizer and control thereof

Details Low jitter digital frequency synthesizer and control thereof Low jitter digital frequency synthesizer and control thereof

2006-11-28

2006-11-28

Anderson, Matthew D. (Department: 2618)

Telecommunications

Transmitter and receiver at same station

With frequency stabilization

C455S075000, C455S083000, C455S260000, C375S371000, C375S374000, C375S376000

Reexamination Certificate

active

07142823

ABSTRACT:
A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates an error value based on the snapshots. The tapped delay line module produces the output clock based on the error value.

REFERENCES:
patent: 5799049 (1998-08-01), McFarland et al.
patent: 6166606 (2000-12-01), Tsyrganovich
patent: 6542040 (2003-04-01), Lesea
patent: 6995621 (2006-02-01), Culler
patent: 7002415 (2006-02-01), Tsyrganovich

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