Low jitter digital delay generator

Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter – Counter chains with a radix or base other than the number...

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Details

377 20, 3281291, 328 58, 307265, H03K 2366, H03K 1923

Patent

active

047260459

ABSTRACT:
A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded including the condition of a lowest order stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.

REFERENCES:
patent: 3391305 (1965-04-01), Bradwin et al.
patent: 3774056 (1973-11-01), Sample et al.
patent: 4467319 (1984-08-01), Uchikoshi
patent: 4622481 (1986-11-01), Nortup

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