Low jitter DDFS FSK modulator

Details Low jitter DDFS FSK modulator Low jitter DDFS FSK modulator

1989-03-03

1991-05-14

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375118, 328 14, H04L 2712

Patent

active

050162594

ABSTRACT:
A low jitter direct digital frequency synthesized frequency shift keyed modulator has a tapped delay line to provide polyphase sampling of an asynchronous data input signal. The samples from the tapped delay line are input to a correction signal generator that produces a correction signal as a function of the location of data transitions in the data input signal with respect to a specified point of a sample clock pulse. The correction signal is used to offset a modulating input to a direct digital frequency synthesizer so that the frequency shift keyed output reflects the data transitions within 1
of the period of the sample clock pulse.

REFERENCES:
patent: 3636477 (1972-01-01), Selz
patent: 3958191 (1976-05-01), Jones, Jr.
patent: 4338571 (1982-07-01), Young
patent: 4492936 (1985-01-01), Albarello et al.
patent: 4618966 (1986-10-01), Stepp et al.
patent: 4628286 (1986-12-01), Nossen
patent: 4670888 (1987-06-01), Smith, III
patent: 4682123 (1987-07-01), Loper et al.
patent: 4700364 (1987-10-01), Miyazaki et al.
patent: 4852124 (1989-07-01), Raucci

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