Pulse or digital communications – Synchronizers – Synchronization failure prevention
Reexamination Certificate
1999-11-18
2002-12-10
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Synchronization failure prevention
C375S355000, C375S356000, C375S376000, C375S287000, C375S219000
Reexamination Certificate
active
06493408
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission apparatus wherein ATM (Asynchronous Transfer Mode) cells are transmitted according to a clock signal generated in synchronization with a clock signal of receiving ATM cells.
FIG. 3
is a block diagram illustrating a conventional example of a data transmission apparatus of this type.
Referring to
FIG. 3
, an optical signal carrying ATM cell data, STM-
1
(Synchronous Transport Module
1
) signal, for example, is transmitted through an optical cable
14
and inputted to an O/E (Optic/Electric) transducer
1
. The O/E transducer
1
converts the optical signal into an electric signal, from which a receiving data signal
3
and a receiving clock signal
4
are extracted and supplied to a receiver-side terminator
2
.
In the receiver-side terminator
2
, a receiving cell-data signal
5
is reproduced from the receiving data signal
3
and the receiving clock signal
4
.
The receiving clock signal
4
is also supplied to a clock generator
31
to be frequency-divided thereby. The output of the clock generator
31
is frequency-multiplied by a clock multiplier
32
and supplied to a digital PLL (Phase Lock Loop)
34
as a reference frequency signal
33
.
Therefore, the frequency of the reference frequency signal
33
can be represented as F/M, F being the frequency of the receiving clock signal
4
and M being a rational number. However, in the following paragraphs, the frequency dividing ratio M is assumed to be a positive integer for simplifying the description.
FIG. 4
is a block diagram illustrating an example of an inner configuration of the digital PLL
34
of
FIG. 3
, comprising a clock oscillator
800
, a controllable frequency divider
801
, a phase comparator
802
and a 1/M frequency divider
804
. When the frequency dividing ratio M is not an integer, the 1/M frequency divider
804
may be replaced with an appropriate combination of a frequency multiplier and a frequency divider.
In the example of
FIG. 4
, the oscillation frequency f of the clock oscillator
800
is designed to be f≈nF, n being a positive integer.
Here, it should be noted that the oscillation frequency f and the. receiving clock frequency F are both subject to their own fluctuation. However, the value of n, and consequently the oscillation frequency f, are so selected as to satisfy a condition f/(n−1)>F>f(n+1).
The controllable frequency divider
801
, consisting of a programmable counter, for example, is controlled to divide the oscillation frequency f by n−1, n or n+1. When the dividing ratio of the controllable frequency divider
801
is controlled to be 1
, an output clock signal
35
of a frequency f
≈F is outputted from the controllable frequency divider
801
, and the output frequency of the 1/M frequency divider
804
becomes almost F/M.
Phases of the output of the 1/M frequency divider
804
and the reference frequency signal
33
(of the frequency F/M) are compared by the phase comparator
802
. When the output phase of the 1/M frequency divider
804
is delayed from the phase of the reference frequency signal
33
, the phase comparator
801
enables an UP signal, which controls the frequency dividing ratio of the controllable frequency divider
801
to be n−1) and the phase of the output clock signal
35
advances.
When the output phase of the 1/M frequency divider
804
is leading from the phase of the reference frequency signal
33
, the phase comparator
801
enables a DOWN signal. By the DOWN signal, the frequency dividing ratio of the controllable frequency divider
801
is controlled to be (n+1), delaying the phase of the output clock signal
35
so that the output phase of the 1/M frequency divider
804
coincides with the phase of the reference frequency signal
33
outputted from the clock multiplier
32
.
Thus, the phase of the output clock signal
35
of the digital PLL
34
is maintained in synchronization with the receiving clock signal
4
.
Returning to
FIG. 3
, a transmitter-side signal generator
10
generates a transmission data signal
11
from a transmission cell data
13
and a transmission clock signal
12
making use of the output clock signal
35
of the digital PLL
34
. The transmission data signal
11
and the transmission clock signal
12
are converted into an optical signal by an E/O (Electric/Optic) transducer
9
and transmitted through an optical cable
15
.
In the conventional data transmission apparatus as above described, there has been a problem that the transmission data signal
11
is affected by jitters of the output clock signal
35
generated by the digital PLL
34
.
As can be easily understood from
FIG. 4
, the frequency of the out-put clock signal
35
may change discontinuously from one of f/(n−1), f
and f/(n+1) to another of them, under control of the phase comparator
802
. This discontinuous change of the output frequency of the digital PLL
34
causes the jitter of the transmission clock signal
12
and when the jitter exceeds its tolerance level, it causes data transmission errors such as cell losses of the data transmission apparatus.
There have been proposed several countermeasures for restraining the jitter of the digital PLL.
By making large the frequency dividing ratio n of the controllable frequency divider
801
together with the oscillation frequency f of the clock oscillator
800
, the jitter amount can be restrained. However, the condition f
−1)>F>f(n+1) can not be satisfied and it becomes difficult for the output frequency of the digital PLL
34
to follow the reference frequency F/M adequately.
In a Japanese patent application laid open as a Provisional Publication No. 166919/'90 entitled “A Digital PLL System”, there is disclosed a digital PLL similar to the digital PLL of
FIG. 4
, which comprises a plurality of controllable frequency dividers
801
. By phase-shifting the output of a clock oscillator
800
, a plurality of clock signals of a frequency f and each having a phase different with each other are generated. Each of the clock signals is supplied to a respective one of the controllable frequency dividers
801
to be frequency-divided by (n−1), n or (n+1). According to output of a phase comparator
802
, output of an appropriate one of the controllable frequency dividers
801
is selected to be outputted as the output clock signal
35
of the digital PLL.
Thus, the jitter amount is restrained in this prior art without enlarging the frequency dividing ratio n.
When the frequency dividing ratio n is made large together with the oscillation frequency f, the pull-in time, which is needed for the phase difference detected by the phase comparator
802
being controlled to zero, becomes long. For dealing with this problem, another prior art is disclosed in a Japanese patent application laid open as a Provisional Publication No. 131492/'95 entitled “A Multi-Relay System”, wherein two digital PLLs are cascade-connected. In the first stage PLL, the oscillation frequency of the clock oscillator is designed to be comparatively low for shortening the pull-in time, while the oscillation frequency of the clock oscillator is designed to be comparatively high in the second stage PLL for restraining the jitter amount.
In still another Japanese patent application laid open as a Provisional Publication No. 326963/'95 entitled “A Digital PLL Circuit”, the jitter amount is restrained without prolonging the pull-in time, by controlling the duration ratio of the controllable frequency divider for dividing the oscillation frequency f by n and n−1, or the duration ratio for dividing by n and n+1, depending on the polarity and the absolute value of the output of the phase comparator.
However, there has been disclosed no idea to control the digital PLL according to the jitter amount actually detected, in any of these prior arts. It is preferable that the jitter amount of the transmission clock signal is as small as possible. However, in practical use, it i
Kumar Pankaj
NEC Corporation
Pham Chi
LandOfFree
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