Low-jitter clock distribution circuit

Details Low-jitter clock distribution circuit Low-jitter clock distribution circuit

2005-01-11

2005-01-11

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

Reexamination Certificate

active

06842136

ABSTRACT:
A low-jitter clock distribution circuit, used in an integrated circuit having multiple analog-to-digital converters (ADCs), includes a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor. The ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter is equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by the semiconductor fabrication process.

REFERENCES:
patent: 6434707 (2002-08-01), Eklof
Rabaey, J. M., “Digital Integrated Circuits: A Design Perspective” Published by Prentice-Hall, Inc., Second Edition, Sep. 2000.

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