Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
1999-01-08
2001-03-13
Patel, T. C. (Department: 2839)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S342000, C029S830000, C029S879000
Reexamination Certificate
active
06200143
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to connectors useful for mounting microelectronic elements and related electronic components, to assemblies made using such connectors and to methods of making such connectors and assemblies, and more particularly, to such connectors having sockets providing low or zero insertion force connection to microelectronic elements and related electronic components.
BACKGROUND OF THE INVENTION
Modern electronic devices utilize microelectronic elements which include semiconductor chips, commonly referred to as “integrated circuits”, which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board. Alternatively, in a “hybrid circuit” one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as “first level” assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a “second level” interconnection.
The structures utilized to provide the first and second level connections must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of input-output connections. Accordingly, the size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. More compact assemblies, with smaller distances between chips provide smaller signal transmission delays and hence permit faster operation of the device.
At present, one widely utilized interconnection method is known as flip-chip bonding. In flip-chip bonding, contacts on the front surface of the chip are provided with bump leads such as balls of solder protruding from the front surface of the chip. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bump leads, is inverted so that its front surface faces toward the top surface of the substrate, with each contact and solder bump lead on the chip being positioned on the appropriate contact pad of the substrate. The assembly is then heated to liquefy the solder and bond each contact on the chip to the confronting contact pad of the substrate.
Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, in flip-chip bonding, the contacts on the chip may be arranged in a so-called “area array” covering substantially the entire front face of the chip. Flip-chip bonding is well suited for use with chips having large numbers of input-output contacts. However, assemblies made by flip-chip bonding are quite susceptible to thermal stresses. The solder interconnections are relatively inflexible, and may be subjected to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips.
One solution has been the use of sockets or spring-like contacts to connect the solder bump leads to the substrate. As microelectronic chips have decreased in size, the pitch of the solder bump lead interconnections has become finer, requiring a finer pitch on mating sockets. At the same time, the mating sockets must still compensate for pitch error and height error in the solder bump leads on the chip. Such accommodation for solder bump lead location tolerances becomes increasingly more difficult as the sockets are more tightly packed in a connector.
U.S. Pat. No. 5,802,699 and Application Ser. No. 08/862,151 filed on May 22, 1997 entitled “Flexible Connectors For Microelectronic Elements”, both assigned to the same assignees as the present application and hereby incorporated by reference herein, disclose sockets having metallic projections arranged circumferentially around a hole for receiving a bump lead. The metallic projections deflect as the solder bump lead is urged into the hole.
Kohn, et al., U.S. Pat. No. 5,199,879 discloses a pin socket having a plurality of deflectable tabs projecting at least partially across an opening. Matsumoto, et al., U.S. Pat. No. 4,893,172 and Noro, et al., U.S. Pat. No. 5,086,337, disclose variants of the flip-chip approach using flexible spring-like elements connected between a chip and a substrate.
Nishiguchi, et al., U.S. Pat. No. 5,196,726 discloses a variant of the flip-chip approach in which non-meltable bump leads on the face of the chip are received in a cup-like sockets on the substrate and bonded therein by a low-melting point material. Beaman, U.S. Pat. No. 4,975,079 discloses a test socket for chips in which dome-shaped contacts on the test substrate are disposed within conical guides. The chip is forced against the substrate so that the solder balls enter the conical guides and engage the dome-shaped pins on the substrate. Enough force is applied so that the dome-shaped pins actually deform the solder balls of the chip.
Rai, et al., U.S. Pat. No. 4,818,728 discloses a first substrate such as a chip with studs or bump leads protruding outwardly and a second substrate with recesses having solder for engaging the bump leads. Malhi, et al., U.S. Pat. No. 5,006,792 discloses a test socket in which a substrate has an exterior ring-like structure and numerous cantilever beams protruding inwardly from the ring-like structure. Contacts are disposed on these cantilever beams so that the same can be resiliently engaged with contacts of a chip when the chip is placed in the socket. Nolan, et al., A Tab Tape-Based Bare Chip Test and Burn Carrier, 1994 ITAP And Flip Chip Proceedings, pp. 173-179 discloses another socket with cantilevered contact fingers for engaging the contacts on a chip; in this case the contact fingers are formed on a flexible tab tape and reinforced by a silicone material so as to provide forcible engagement and a wiping action with the chip contact.
Despite all of these efforts in the art, however, there have still been needs for improved connectors for connecting microelectronic elements and other related electronic components suitable for use in providing first and second level interconnection in the making of modern electronic devices. More particularly, there is an unsolved need for such connectors which include sockets for receiving solder bump leads for electrical connection thereto using low or zero insertion force to prevent any possible damage to the microelectronic element.
SUMMARY OF THE INVENTION
The present invention discloses the formation of socket-like structures on a support such as a dielectric sheetlike layer having top and bottom surfaces, and further including patterned metallic layers on the top and bottom surfaces. The resulting two-sided metal laminate may be formed by adhering metal foil to both sides of a dielectric layer, or may be formed by plating or sputtering a metal to both sides of the dielectric layer.
One process for forming a socket-like structure using the two-sided laminate includes initially etching an opening in the top metal layer. The dielectric layer is then etched through the opening typically using a
Faraci Anthony B.
Haba Belgacem
Lerner David Littenberg Krumholz & Mentlik LLP
Patel T. C.
Tessera Inc.
LandOfFree
Low insertion force connector for microelectronic elements does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low insertion force connector for microelectronic elements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low insertion force connector for microelectronic elements will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2526961