Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
1999-03-11
2001-02-13
Monin, Jr., Donald L. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S034000, C257S031000, C438S002000
Reexamination Certificate
active
06188084
ABSTRACT:
BACKGROUND
The present invention relates to a low inductance superconductive integrated circuit and a method of fabricating the same, and in particular to a niobium nitride (NbN) based superconductive integrated circuit with reduced circuit inductances.
At the present time, there are two major types of superconductive integrated circuits, one of which uses niobium (Nb) and the other uses niobium nitride (NbN). Nb-based superconductive integrated circuits generally have low parasitic circuit inductances, and are therefore suitable for high-speed and high-frequency operations. However, a disadvantage of the Nb-based superconductive integrated circuits is that the temperature required for the operation of such circuits is close to 4 K, which necessitates the use of liquid helium. Liquid helium requires complicated and expensive refrigerating systems. On the other hand, NbN-based superconductive integrated circuits have been developed for operation at temperatures above the liquid helium temperature. NbN-based circuits can operate at a temperature of 10 K or higher, which can be achieved and maintained by a relatively simple closed-cycle refrigerator.
However, typical thin films of NbN used in the fabrication of superconductive integrated circuits exhibit relatively large penetration depth in the range of about 250-350 nm. A large penetration depth gives rise to high parasitic inductances in the NbN-based superconductive integrated circuit which degrades circuit speed and performance. Conventional NbN-based integrated circuits generally have slower operational speeds than those of Nb-based integrated circuits.
Another disadvantage of conventional NbN-based superconductive integrated circuits is that their circuit densities are generally low. A typical NbN process has only a low value resistor with a sheet resistance in the range of about 0.5-2 ohms/square. In the conventional process, the low value resistor can only be connected to the circuit through a second level metal. There are two disadvantages associated with this arrangement. First, the second level metal has an undesirable parasitic inductance which reduces the circuit speed. Second, because of the low sheet resistance, a large circuit resistance requires a large number of squares which consume a significant amount of the circuit's surface area, thereby decreasing the circuit density.
Therefore, there is a need for a NbN-based superconductive integrated circuit that has low parasitic circuit inductances to enable high-speed operations. Furthermore, there is a need for increasing the circuit density to reduce circuit area so that larger scale integration can be achieved.
SUMMARY OF THE INVENTION
The present invention satisfies these needs. In view of the above problems, the present invention provides a NbN-based superconductive integrated circuit that has low parasitic circuit inductances and a high circuit density, and a method of fabricating the same. The superconductive integrated circuit generally comprises:
(a) a superconductive ground plane having a ground plane surface;
(b) a plurality of superconductive interconnect wire layers including a first wire layer and a second wire layer, the wire layers each having a plurality of interconnect wires, and the interconnect wires of the first wire layer having a plurality of contacts including at least one tunnel junction contact;
(c) an interlevel dielectric on the ground plane surface, the interlevel dielectric having contoured outer and inner surfaces that are adapted to accept the first and second wire layers;
(d) at least one superconductive base electrode having at least one tunnel junction and at least one contact to provide a conductive path between the base electrode and tunnel junction, the base electrode having an interconnect inductance;
(e) at least one tunnel barrier on the base electrode;
(f) at least one superconductive counter electrode connected between at least one of the interconnect wires of the first wire layer and the tunnel barrier;
(g) at least one low value resistor within the interlevel dielectric, the low value resistor connected between at least two of the interconnect wires and positioned with respect to the tunnel junction to reduce the interconnect inductance; and
(h) at least one high value resistor connected between at least two of the interconnect wires to provide a sheet resistance substantially higher than that of the low value resistor, thereby reducing the physical size of the resistor and surface area of the integrated circuit.
The present invention also provides a method of fabricating the superconductive integrated circuit. The method generally comprises the steps of:
(a) providing a patterned ground plane;
(b) depositing and patterning a first dielectric layer on the ground plane;
(c) depositing a trilayer consisting essentially of a base electrode, a tunnel barrier, and a counter electrode on the first dielectric layer;
(d) patterning and etching the superconductive counter electrode upon the tunnel barrier and removing the tunnel barrier everywhere except under the counter electrode and in the vicinity of the counter electrode;
(e) patterning and etching the superconductive base electrode on the first dielectric layer;
(f) depositing a second dielectric layer on the base electrode and the counter electrode;
(g) depositing and patterning at least one low value resistor in the second dielectric layer, the low value resistor being positioned to connect at least two of the first interconnect wires;
(h) depositing a third dielectric layer to insulate a portion of the low value resistor, and patterning and etching contacts to the low value resistors;
(i) patterning and etching contacts in the second and third dielectric layers to contact the base electrode and the counter electrode;
(j) depositing and patterning the first wire layer in the dielectric layers so that at least some of the interconnect wires of the first wire layer are electrically connected with the counter electrode, the base electrode, the low value resistor, and the ground plane;
(k) depositing and patterning at least one high value resistor that is adapted to connect with at least two of the interconnect wires;
(l) depositing a fourth dielectric layer to partially insulate the second wire layer and the high value resistor, the first, second, third and fourth dielectric layers together forming an interlevel dielectric, and patterning and etching contacts in the fourth dielectric layer; and
(m) depositing and patterning the second wire layer at selected locations on the first wire layer and the interlevel dielectric so that at least some of the interconnect wires of the second wire layer have electrical contact with the first wire layer and the high value resistor.
The present invention is applicable to trilayer superconductive integrated circuits, and is particularly applicable to NbN/MgO/NbN-based integrated circuits. The ground plane preferably comprises NbN, and the interlevel dielectric layer preferably comprises silicon dioxide (SiO
2
). The low value resistor is made of a low resistance metallic material, preferably molybdenum (Mo). The high value resistor provides a high sheet resistance and is preferably made of a metallic, non-superconducting compound of NbN
x
.
Advantageously, the low value molybdenum resistors having a sheet resistance of approximately 1 ohm/square, are typically used to shunt junctions with first interconnect wires, are placed adjacent the junction contacts to reduce the shunted junction inductance. Moreover, the high value NbN
x
resistors are preferably positioned to connect the interconnect wires of the second NbN wire layer. It is further preferred that the high value NbN
x
resistor be deposited through a liftoff mask which allows it to be fabricated at the same level above the NbN ground plane as a first NbN interconnect wire layer. One of the interconnect wires of the second wire layer can have a direct contact with the ground plane through one of the interconnect wires of the first wire layer and base electrode, and the contact
Abelson Lynn A.
Elmadjian Raffi N.
Kerber George L.
Ladizinsky Eric G.
Monin, Jr. Donald L.
TRW Inc.
Wille Douglas A.
Yatsko Michael S.
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