Low inductance power wiring structure and semiconductor device

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Reexamination Certificate

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C257S299000, C257S723000, C363S016000, C363S123000, C363S131000

Reexamination Certificate

active

06501167

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a low-inductance wiring structure with semiconductor switching elements, applicable to a power inverter.
2. Description of the Related Art
When two wide electrodes are laid one upon another with an insulator interposing between them and currents that are oppositely directed are passed through the electrodes, respectively, magnetic fields produced around the electrodes by the currents cancel each other, to reduce the inductance of the electrodes. This phenomenon is widely known. Based on this phenomenon, Japanese Unexamined Patent Publication No. 6-38507 discloses a technique of layering a high-potential power bus P and a low-potential power bus N to form a two-layer electrode structure capable of reducing inductance.
The two-layer electrode structure involving power buses P and N is applicable to an inverter module having an integrated inverter circuit, to reduce inductance. In practice, however, the two-layer structure does not always pass opposite currents of the same value because the buses P and N in the two-layer structure must supply a current to load through an output line U. In a real inverter module, a current forms a loop as shown in FIG.
1
. The inverter module
1
of
FIG. 1
involves two phases U and V. In each of U- and V-phase circuits, buses P and N are arranged to face each other with an insulator interposing between them. This configuration forms a current path indicated with a thick black lines and a looped current path indicated with a large dotted arrow mark depicted by C. Namely, opposite currents to cancel magnetic fields flow only in dotted circle areas A and B outside the inverter module
1
. Inside the inverter module
1
, magnetic fields do not cancel each other. Consequently, the example of
FIG. 1
is insufficient to provide the effect of reducing wiring inductance.
When a switching element in an inverter is turned on and off, it generates a surge voltage V=−L·di/dt that is proportional to inductance L. If the inductance of wiring is large, a large surge voltage is produced to break the switching element. To prevent the breakage of switching elements, a snubber may be arranged. The snubber, however, increases the number of parts, to increase the size and cost of the inverter. Instead of employing the snubber, the surge voltage is suppressible by slowing down a switching speed. This, however, hinders high-frequency switching and elongates a switching time to increase switching loss and heat. The heat needs a large radiator to cool and deteriorates efficiency.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a power wiring structure of low inductance.
Another object of the present invention is to provide a semiconductor device employing such a power wiring structure.
In order to accomplish the objects, an aspect of the present invention provides a power wiring structure employing two switching elements connected in series and complementarily turned on and off, power lines extending from a power source to one ends of the switching elements, and an output line extending from a node between the switching elements to load. The power lines include a high-potential power line P and a low-potential power line N. The output line is an output line U. The lines P, N, and U are each a wide electrode with the width thereof being greater than the thickness thereof. These lines are layered one upon another in order of P, U, and N with an insulator interposed between adjacent ones of the layered lines, to form a three-layer wide electrode structure. The two switching elements that are connected in series and are complementarily turned on and off correspond to, for example, an inverter circuit, an H-bridge circuit employing two inverters connected in parallel with each other, and a three-phase inverter circuit employing three inverter circuits connected in parallel with one another.
Assuming that there is no current leakage, opposite currents of the same value flow through the output line U and one of the power lines P and N, to cancel magnetic fields generated around the lines by the currents, thereby effectively reducing wiring inductance.
Another aspect of the present invention employs the three-layer wide electrode structure mentioned above and arranges wiring such as bonding wires in an inverter module in such a way as to cancel magnetic fields generated by currents flowing through the wiring, thereby effectively reducing the inductance of the wiring in the inverter module.


REFERENCES:
patent: 5499186 (1996-03-01), Carosa
patent: 5544035 (1996-08-01), Beriger et al.
patent: 5719759 (1998-02-01), Wagner et al.
patent: 5808240 (1998-09-01), Czerwinski et al.
patent: 5942797 (1999-08-01), Terasawa
patent: 6181590 (2001-01-01), Yamane et al.
patent: 6255008 (2001-07-01), Iwase
patent: 02-188189 (1990-07-01), None
“Intelligent IGBT Module for the Hybrid Vehicle”, Y. Nii et al., Society of Automotive Engineers of Japan, Inc., Proceeding of Conference 982, 1998, pp. 61-64 (Month Unknown).

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