Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
1999-11-04
2001-04-03
Riley, Shawn (Department: 2838)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S666000, C257S676000
Reexamination Certificate
active
06211462
ABSTRACT:
CROSS REFERENCE TO APPLICATIONS
This application is related to U.S Pat. No. 5,594,234 granted on Jan. 14, 1997 and to U.S. Pat. No. 5,663,597 granted on Sep. 2, 1997.
FIELD OF THE INVENTION
This invention relates to semiconductor devices, more particularly to packaging of semiconductor devices, and more particularly to a package having low lead inductance.
BACKGROUND OF THE INVENTION
High frequency telecommunications semiconductor devices for low impedance RF transmission circuits require very low inductance interconnections between the chip and the circuit board. Frequently, integrated circuits designed for these applications are also relatively high power devices. Semiconductor devices that dissipate high power, or are used in high frequency telecommunications, are usually packaged with a heat sink to dissipate heat produced by the device and to provide a RF ground plane for the device. The heat sink is positioned close to or against the semiconductor device and is encapsulated within the device package with one surface of the heat sink exposed through the package encapsulant. The addition of a heat sink along with a lead frame requires additional components, additional assembly steps, and additional equipment, thereby increasing the cost of the device.
Previously, packages for RF transmission circuits included hermetic packages for military application, and more recently packages having the die mount pad of the leadframe exposed through the plastic encapsulant, or having a custom leadframe with wide ground connections. The latter packages make attempts to compensate for the shortcomings of known high frequency and/or high power packages, and have been disclosed in U.S. Pat. No. 5,594,234 issued Jan. 14, 1997 and U.S. Pat. No. 5,663,597 issued on Sep. 2, 1997.
In high frequency applications the semiconductor package has the greatest influence on total performance of the circuit, and one of the main causes of performance degradation is inductance of the interconnections between chip and printed wiring board. Therefore, as the operating frequency of these circuits increases there is a need for even lower inductance packages, some of which may require less than 50 ohms matched impedance.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a novel packaging structure for integrated circuits having very low inductance and an RF ground plane. The above and other objects, features and advantages will be apparent from the following descriptions.
It is further an object of the invention that the package design is readily expandable to families of packages having common design features rather than customized packages.
Still further, an object of the current invention is to provide a package having high thermal dissipation.
It is also an object of this invention that the package be small, and be near chip sized. While the package will consume a minimal amount of board space, it is an object of the invention that leads external to the package be designed to allow inspection of solder joints after been soldered to a printed circuit board.
Another object of the current invention is that the package be constructed of low cost materials, and low cost assembly processes, in order to meet the cost requirements of the consumer market. It is an object of the invention that the package be reliable, and easily manufactured.
It is an object of the invention that the inductance and thermal objectives of the package be met without the need for additional components, such as in-package capacitors.
The above objectives are met by a packaging structure wherein the die is mounted on a flat, relatively thick, non-magnetic leadframe having a die mount pad which is exposed through the under side of the package. The lead tips inside the package are elevated in order to be in very close proximity to bond pads on the die, and thereby minimizing the length of bond wire necessary to connect bond pads to leads. The external lead tips are parallel to the die mount pad and extend beyond the package edge, so that solder connections can be easily inspected after the package has been assembly onto a printed wiring board.
Features are included in the leadframe design to support locking of the encapsulating mold compound to the leadframe, and to support heavy clamping of the mold in order to avoid flashing or bleed of the plastic onto the leads and exposed die mount pad.
A family of package designs for rectangular dual lead small outline packages, as well as a family of 16 through 40 pin square or quad surface mount packages are disclosed as exemplary; however the invention is not limited to these package families or types.
The package construction on the top side of the leadframe allows a simple mold design requiring no intermeshing of the plastic above and below the leadframe. In further support of low cost assembly objectives, straight external leads require no forming operation or equipment. In addition, the packages are designed for “in line” handlers, and thereby avoid the need for slow, high cost pick and place equipment.
The drawings constitute a part of this specification and include exemplary embodiments of the invention which may be embodied in various forms. It is to be understood that in some instances aspects of the invention may be shown exaggerated or enlarged to facilitate understanding of the invention.
REFERENCES:
patent: 5479050 (1995-12-01), Pritchard et al.
patent: 5594234 (1997-01-01), Carter, Jr. et al.
patent: 5663597 (1997-09-01), Nelson et al.
Carter, Jr. Buford H.
Davis Dennis D.
Honeycutt Gary C.
Navarro Arthur I.
Riley Shawn
Telecky Fred
Texas Instruments Incorporated
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