Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1998-06-18
2004-12-07
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S697000
Reexamination Certificate
active
06828666
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to power distribution, and more particularly, to a low impedance power distribution system for an integrated circuit chip.
2. Description of the Related Art
The electrical coupling of an integrated circuit such as a microprocessor to a power supply can be modeled as a resistance-inductance-capacitance (RLC) circuit. A series of conductive paths define a power supply loop circuit from a first terminal of the power supply to the integrated circuit and back from the integrated circuit to a second terminal of the power supply. The electrical characteristics of these conductors (e.g., resistance, capacitance and inductance) and their configuration define the AC impedance of the loop circuit.
A well designed power distribution system should provide a well-regulated supply voltage over a wide range of frequencies from a peak frequency, down through mid-frequencies, to very low frequencies characterized by sleep modes. Unfortunately, even well designed power distribution systems will exhibit an imperfect, i.e., non-uniform, AC impedance as a function of frequency. As high performance integrated circuits demand larger currents at higher frequencies with lower power supply voltages, power system design becomes increasingly more challenging. For example, next generation microprocessors will demand peak currents in excess of 100 A and reach operating frequencies of 1 GHz with power supply voltages below 2 V. At such current levels, surge currents and associated excitations of power distribution system resonances can result in significant power supply voltage excursions. Accordingly, reductions in the AC impedance of a power distribution system, particularly inductive components thereof, are desired.
A variety of techniques are available to improve the AC impedance characteristics of a power distribution system. One such technique involves the appropriate placement of decoupling structures/devices, e.g., capacitors, throughout the power distribution system. Others include chip layout with respect to power distribution, use of low inductance packaging technologies such as Controlled Collapse Chip Connection (C4) and Ball Grid Array (BGA) for delivery of supply voltages (V
DD
and V
SS
), BGA package design and layers, card layout and use of discrete capacitance placed thereon, connector selection and V
DD
/V
SS
allocations, regulator choice, and lastly the motherboard layout.
In a typical computer system “Slot 1” configuration, inductances are associated with the vias, traces, connectors, etc. of an integrated circuit carrier (or “package”), of a daughterboard card, and of a motherboard. At low frequencies (i.e., below approximately 100 KHz), impedance of the power supply loop circuit can be made arbitrarily low through the utilization of feedback voltage sensing at the power supply. At very high frequencies, the impedance of the power supply loop circuit can be lowered with the use of on-die capacitance to approximately (1/&ohgr;C) where &ohgr; is the angular frequency (such that &ohgr;=2&pgr;f) and C is the capacitance associated with the power supply loop circuit including the on-die capacitance. Unfortunately, in the mid-frequencies (e.g., from approximately 1 MHz to 100 MHz), the AC impedance of the power supply loop circuit is likely to exhibit resonances.
While the impedance at both high- and mid-frequencies can be managed through the use of decoupling capacitors placed strategically in the power supply loop circuit, two significant challenges exist. First, spatial limitations of an integrated circuit chip can limit the amount of capacitance provided on-die. Typically, only portions of the die that are free from device structures will be available for fabrication of on-die capacitors. High-frequency, high-current integrated circuits such as advanced microprocessors may require hundreds of nF of on-die capacitance. Such capacitance typically requires a significant die footprint, since with typical gate oxide thicknesses the capacitance is of the order of 10 nF per mm
2
. As a result, achieving such added capacitance can adversely affect die size and yield. Even worse, larger capacitances, e.g., &mgr;F, will be required to manage mid-frequency resonances. Second, F although resonance peaks in the impedance at mid-frequencies can be lowered by off-chip decoupling capacitors, the inductive impedance of off-chip portions of the power supply loop circuit typically limits the efficacy of large off-chip capacitors. In general, the series inductance (L
s
) from the switching circuits of the integrated circuit to the decoupling capacitance (C
p
) should be low enough that the decoupling capacitance pathway resonance,
1
2
π
C
p
L
s
,
is in the range of mid-frequency resonances to be mitigated, e.g., 1-100 MHz. Accordingly, power distribution configurations are desired in which large, e.g., tens to thousands nF, can be placed off-chip but with low intervening inductance.
SUMMARY OF THE INVENTION
It has been discovered that providing an integrated circuit chip carrier with a power supply loop having first and second groups of carrier vias arranged in an anti-parallel tessellation advantageously reduces the inductance of a loop circuit associated with the first and second groups of carrier vias. By providing two large-numbered carrier via groups with complementary current flows in an anti-parallel tessellation, the inductance of an electrical pathway between an integrated circuit chip and decoupling capacitance can be greatly reduced. The reduction in the inductance of the electrical pathway allows large off-chip and off-package decoupling capacitance to be used to effectively manage mid-frequency resonances. For example, in one embodiment in accordance with the invention, the inductance of an electrical pathway from decoupling capacitance located on one side of a circuit board, through a circuit board, through a carrier, and to the integrated circuit is less than 60 pH.
In one aspect of the invention, an apparatus includes an integrated circuit carrier, a circuit board, and a loop circuit having a loop inductance. The integrated circuit carrier includes first and second power planes, first and second groups of carrier vias extending from the first and second power planes, respectively, substantially to a first side of the carrier, and third and fourth groups of carrier vias extending from the first and second power planes, respectively, substantially to a second side of the carrier. The circuit board includes first and second groups of circuit board vias extending substantially from a first side of the circuit board towards a second side of the circuit board. The loop circuit is defined from the first group of circuit board vias, through the third group of carrier vias, through the first power plane, through the first group of carrier vias to the first side of the circuit board and back through the second group of carrier vias, through the second power plane, through the fourth group of carrier vias, through the second group of circuit board vias. The carrier vias of the first and second groups are arranged in an anti-parallel tessellation, and the circuit board vias of the first and second groups are arranged in an anti-parallel tessellation.
In another aspect, the invention includes a method of providing a low inductance path through a carrier for an integrated circuit. The method includes positioning first and second power planes between first and second sides of an integrated circuit carrier. The method also includes positioning first and second groups of carrier vias extending from the first and second power planes, respectively, substantially to the first side in an anti-parallel tessellation to reduce a loop inductance associated with the first and second carrier vias for a loop circuit defined from a first group of electrically conductive structures on the second side though the first power plane, through the first group of carrier vias, back through the second group of carrier vias, t
Dolbear Thomas P.
Herrell Dennis J.
Advanced Micro Devices , Inc.
Cao Phat X.
Zagorin O'Brien & Graham LLP
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